Robert Allan JamesandClaude Opus 5.5
7252e2ed72
Every lock carries a rank (hermes < switch < registry < VM dict_lock < VM tuning_lock < stadium < slot < doe < log < block < console < heap < vmm < pmm); each core counts held locks per rank and an acquisition not above the highest held rank counts an order violation, reported in full at the idle point. Probe inversion reported exactly once; O-A, a 28-VM churn and the standard sequence show 0 violations on all three ISAs. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
110 lines
4.3 KiB
C
110 lines
4.3 KiB
C
/*
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StarForth — Steady-State Virtual Machine Runtime
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Copyright (c) 2023–2025 Robert A. James
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All rights reserved.
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This file is part of the StarForth project.
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Licensed under the StarForth License, Version 1.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at:
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https://github.com/star.4th@proton.me/StarForth/LICENSE.txt
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This software is provided "AS IS", WITHOUT WARRANTY OF ANY KIND,
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express or implied, including but not limited to the warranties of
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merchantability, fitness for a particular purpose, and noninfringement.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* percpu.h - Per-core state (FABRIC-3.10.8 Stage MC-0a).
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*
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* Each core owns one sk_percpu_t, reached through that ISA's per-CPU
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* register, so code running on a core -- including an interrupt handler --
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* finds its own block without a lookup:
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* - amd64: the GS base (IA32_GS_BASE); the block's first field points
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* back at itself, so `mov %gs:0` reads the pointer.
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* - aarch64: TPIDR_EL1 (reachable from EL2 as well, so either boot EL).
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* - riscv64: the tp register (the kernel owns it: no user mode, no TLS;
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* the trap entry never touches it).
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*
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* MC-0a: only the boot core exists, and its block is a single statically
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* allocated object (not a table of cores -- secondary cores' blocks are
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* allocated as they come online, MC-1). What moves in first is the switch
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* mechanism's "who is running on this core" (was switch.c's global
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* g_switch_current_vm).
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*/
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#ifndef STARKERNEL_PERCPU_H
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#define STARKERNEL_PERCPU_H
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#include <stdint.h>
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#include "starkernel/spinlock.h" /* SK_LOCK_RANK_COUNT */
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struct VM;
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typedef struct sk_percpu {
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struct sk_percpu *self; /* must stay first: amd64 reads it as %gs:0 */
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uint32_t core_id; /* 0 = the boot core (the system core, MC-R1) */
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struct VM *current_vm; /* who is running on this core (switch.c) */
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/* MC-0b (spinlock.c): locks this core holds right now, and the
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* interrupt state to restore when that count returns to 0. Kept here,
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* not in each lock, so interrupts come back correctly whatever order
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* the locks are released in. */
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uint32_t lock_depth;
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uint64_t saved_irq;
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uint64_t lock_acquired; /* every acquire on this core, ever */
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uint64_t lock_released; /* every release on this core, ever */
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/* K-11 (spinlock.c): locks this core holds right now, per rank -- the
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* lock-order check compares a new lock's rank with the highest held. */
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uint32_t held_rank[SK_LOCK_RANK_COUNT];
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} sk_percpu_t;
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/* Installs the boot core's block in this core's per-CPU register. Call
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* once, as early as possible (kernel_main, straight after
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* arch_early_init(): on amd64 that reloads GS, which would reset the base). */
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void sk_percpu_boot_init(void);
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/* 1 once the boot core's block is installed (MC-0b). Before that the
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* per-CPU register still holds whatever the firmware left there -- on
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* riscv64 the monolithic loader's kernel_main() prints from
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* arch_early_init() with tp still the firmware's -- so the spinlocks
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* (spinlock.c) do nothing until it is set: early boot is one core with
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* interrupts off. */
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extern volatile int sk_percpu_ready;
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/* This core's block. Valid from sk_percpu_boot_init() on. */
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static inline sk_percpu_t *sk_percpu(void)
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{
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sk_percpu_t *p;
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#if defined(__x86_64__)
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__asm__ volatile ("movq %%gs:0, %0" : "=r"(p));
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#elif defined(__aarch64__)
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__asm__ volatile ("mrs %0, tpidr_el1" : "=r"(p));
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#elif defined(__riscv)
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__asm__ volatile ("mv %0, tp" : "=r"(p));
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#else
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#error "percpu.h: unsupported architecture"
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#endif
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return p;
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}
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/* Architecture hook: point this core's per-CPU register at `p`. */
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static inline void sk_percpu_install(sk_percpu_t *p)
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{
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#if defined(__x86_64__)
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uint64_t v = (uint64_t)(uintptr_t)p;
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__asm__ volatile ("wrmsr" : : "c"(0xC0000101u) /* IA32_GS_BASE */,
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"a"((uint32_t)v), "d"((uint32_t)(v >> 32)) : "memory");
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#elif defined(__aarch64__)
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__asm__ volatile ("msr tpidr_el1, %0" : : "r"(p) : "memory");
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#elif defined(__riscv)
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__asm__ volatile ("mv tp, %0" : : "r"(p) : "memory");
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#endif
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}
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#endif /* STARKERNEL_PERCPU_H */
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