Robert Allan JamesandClaude Opus 5.5
3a2ba5149f
Cores from the DTB /cpus or, on QEMU (ACPI, no DTB), the MADT GICC entries; the MADT lookup is now shared (hal/acpi.c) with amd64. PSCI CPU_ON through the discovered conduit into ap_entry.S, which copies the boot core's MMU/control state, sets TPIDR_EL1 and parks. Core 1 online at EL1 with its own block; its vCPU thread 0.0% on the host. QEMU aarch64 -smp 2 -name debug-threads=on. 3-ISA acceptance clean. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
71 lines
1.9 KiB
ArmAsm
71 lines
1.9 KiB
ArmAsm
/*
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* ap_entry.S (aarch64) -- secondary-core entry, FABRIC-3.10.8 MC-1b.
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*
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* PSCI CPU_ON lands here at EL1 with the MMU and caches off and
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* x0 = the core's boot block (arch/aarch64/smp.c: a64_boot_t; the kernel
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* is identity-mapped, so its address is physical too). The boot core has
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* cleaned the block to the point of coherency, since these first loads
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* bypass the caches.
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*
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* The core takes the boot core's own translation and control state --
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* MAIR, TCR, TTBR0/1, VBAR, CPACR (FP/SIMD: kernel C uses it) -- then
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* SCTLR, which turns the MMU and caches on at this same, identity-mapped
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* address. It sets TPIDR_EL1 to its per-core block before any C code,
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* records CurrentEL, and calls sk_smp_secondary_main(block) on its own
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* stack. No symbol is referenced: every address comes from the block
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* (this file is also assembled for the PE/COFF loader).
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*/
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.section .text
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.balign 4
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.equ B_MAIR, 0
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.equ B_TCR, 8
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.equ B_TTBR0, 16
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.equ B_TTBR1, 24
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.equ B_VBAR, 32
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.equ B_CPACR, 40
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.equ B_SCTLR, 48
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.equ B_PERCPU, 56
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.equ B_STACK, 64
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.equ B_ENTRY, 72
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.equ B_EL, 80
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.global sk_ap_entry_a64
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sk_ap_entry_a64:
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msr daifset, #0xf
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mov x19, x0
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ldr x1, [x19, #B_MAIR]
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msr mair_el1, x1
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ldr x1, [x19, #B_TCR]
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msr tcr_el1, x1
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ldr x1, [x19, #B_TTBR0]
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msr ttbr0_el1, x1
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ldr x1, [x19, #B_TTBR1]
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msr ttbr1_el1, x1
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ldr x1, [x19, #B_VBAR]
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msr vbar_el1, x1
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ldr x1, [x19, #B_CPACR]
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msr cpacr_el1, x1
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isb
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tlbi vmalle1
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dsb nsh
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ic iallu
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dsb nsh
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isb
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ldr x1, [x19, #B_SCTLR]
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msr sctlr_el1, x1
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isb
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ldr x1, [x19, #B_PERCPU]
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msr tpidr_el1, x1
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ldr x1, [x19, #B_STACK]
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mov sp, x1
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mrs x2, CurrentEL
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str x2, [x19, #B_EL]
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ldr x3, [x19, #B_ENTRY]
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ldr x0, [x19, #B_PERCPU]
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blr x3
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1:
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wfi
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b 1b
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