Cores from the DTB /cpus or, on QEMU (ACPI, no DTB), the MADT GICC entries; the MADT lookup is now shared (hal/acpi.c) with amd64. PSCI CPU_ON through the discovered conduit into ap_entry.S, which copies the boot core's MMU/control state, sets TPIDR_EL1 and parks. Core 1 online at EL1 with its own block; its vCPU thread 0.0% on the host. QEMU aarch64 -smp 2 -name debug-threads=on. 3-ISA acceptance clean. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
src/starkernel/arch/aarch64/
AArch64 architecture support for LithosAnanke.
arch.c— architecture init entry point.apic.c— GIC (Generic Interrupt Controller) stub, namedapic.cto match the shared per-arch file-naming convention across amd64/aarch64/riscv64. Satisfies the commonapic_init()/apic_eoi()call sites without real GIC bring-up yet; deferred to a later milestone.timer.c— architected timer setup (heartbeat tick source).interrupts.c— exception vector table setup and interrupt dispatch.boot.S— early boot assembly.isr.S— interrupt service routine stubs.
No kernel_entry.S — aarch64 uses a different UEFI loader entry path
(clang/lld-link COFF target, since GCC cannot produce an aarch64 PE
image; see Makefile.starkernel).