FABRIC-3.10.8 MC-3b: waking a worker core

Each worker core sets up its own IPI receiver before going online (amd64
LAPIC + vector 0x22 with its own stub, aarch64 banked GIC SGI 0, riscv64
sie.SSIE); core 0 sends by ICR / GICD_SGIR / SBI IPI. Park lets exactly
one interrupt in without a lost-wake window. Boot self-test: IPI round
trips 3/3 and 'woke x3, IPIs x3' on all three ISAs; worker vCPU threads
0.0% on the host. 3-ISA acceptance clean.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>

include/starkernel/apic.h

@@ -60,6 +60,11 @@
  * before, so this path was previously dormant. */
 #define APIC_SPURIOUS_VECTOR 0xFF
 
+/* amd64 (FABRIC-3.10.8 MC-3b): the inter-processor wake vector. Needs its
+ * own stub in isr.S -- vectors past 33 otherwise land in the default stub,
+ * which reports 255. */
+#define SK_IPI_VECTOR 0x22
+
 /* Initialize Local APIC (enables APIC, sets spurious vector) */
 int apic_init(BootInfo *boot_info);
 
@@ -72,6 +77,10 @@ uint8_t apic_id(void);
  * Returns 0 once delivered, -1 if still pending after the bound. */
 int apic_send_ipi(uint8_t dest_apic_id, uint32_t icr_low);
 
+/* amd64 (MC-3b): on a secondary core, enable its own LAPIC (SIVR, TPR 0)
+ * so it can take SK_IPI_VECTOR. Its timer LVT stays masked. */
+void apic_secondary_enable(void);
+
 /* Send End-of-Interrupt signal */
 void apic_eoi(void);
 

include/starkernel/percpu.h

@@ -73,6 +73,10 @@ typedef struct sk_percpu {
     struct VM        *release_after;
     volatile uint32_t decision_due;
     struct VM        *entry_vm;      /* the VM a first-entry trampoline starts as */
+    /* MC-3b (hal/smp.c): how to reach this core with an IPI (the APIC id,
+     * the GIC target mask, the hartid), and how many it has received. */
+    uint64_t          ipi_target;
+    volatile uint64_t ipi_received;
 } sk_percpu_t;
 
 /* Installs the boot core's block in this core's per-CPU register. Call

include/starkernel/smp.h

@@ -64,4 +64,16 @@ void arch_smp_park_once(void);
  * exception level, the privilege mode), as a short phrase for its line. */
 const char *arch_smp_arrival(const sk_percpu_t *pc);
 
+/* MC-3b. On the secondary core, before it reports online: set up its own
+ * interrupt receiver for the IPI only, and record in pc->ipi_target how
+ * to reach it. */
+void arch_smp_secondary_init(sk_percpu_t *pc);
+
+/* MC-3b. Send the wake IPI to the core `target` describes. */
+void arch_smp_send_ipi(const sk_percpu_t *target);
+
+/* MC-3b. Called by each ISA's interrupt handler when the IPI arrives: counts
+ * it in this core's block. The handler acknowledges it. */
+void sk_smp_ipi_received(void);
+
 #endif /* STARKERNEL_SMP_H */