Robert Allan JamesandClaude Opus 5.5
71e0be96b0
Each worker core sets up its own IPI receiver before going online (amd64 LAPIC + vector 0x22 with its own stub, aarch64 banked GIC SGI 0, riscv64 sie.SSIE); core 0 sends by ICR / GICD_SGIR / SBI IPI. Park lets exactly one interrupt in without a lost-wake window. Boot self-test: IPI round trips 3/3 and 'woke x3, IPIs x3' on all three ISAs; worker vCPU threads 0.0% on the host. 3-ISA acceptance clean. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
121 lines
4.0 KiB
C
121 lines
4.0 KiB
C
/*
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StarForth — Steady-State Virtual Machine Runtime
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Copyright (c) 2023–2025 Robert A. James
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All rights reserved.
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This file is part of the StarForth project.
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Licensed under the StarForth License, Version 1.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at:
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https://github.com/star.4th@proton.me/StarForth/LICENSE.txt
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This software is provided "AS IS", WITHOUT WARRANTY OF ANY KIND,
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express or implied, including but not limited to the warranties of
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merchantability, fitness for a particular purpose, and noninfringement.
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See the License for the specific language governing permissions and
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limitations under the License.
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StarForth — Steady-State Virtual Machine Runtime
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Copyright (c) 2023–2025 Robert A. James
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All rights reserved.
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This file is part of the StarForth project.
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Licensed under the StarForth License, Version 1.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at:
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https://github.com/star.4th@proton.me/StarForth/LICENSE.txt
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This software is provided "AS IS", WITHOUT WARRANTY OF ANY KIND,
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express or implied, including but not limited to the warranties of
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merchantability, fitness for a particular purpose, and noninfringement.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* apic.h - Local APIC interface
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*/
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#ifndef STARKERNEL_APIC_H
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#define STARKERNEL_APIC_H
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#include "uefi.h"
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#include <stdint.h>
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/* Heartbeat timer vector (user-defined IRQ space starts at 0x20) */
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#define APIC_TIMER_VECTOR 0x20
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/* Spurious-interrupt vector (APIC_REG_SIVR, set in apic_init()). A normal,
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* occasional hardware race per Intel SDM Vol.3 §10.9 -- not a fault. Must
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* be silently ignored with no EOI. Surfaced by item 4.3.5's I/O APIC work:
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* no real external interrupt had ever been delivered through the I/O APIC
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* before, so this path was previously dormant. */
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#define APIC_SPURIOUS_VECTOR 0xFF
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/* amd64 (FABRIC-3.10.8 MC-3b): the inter-processor wake vector. Needs its
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* own stub in isr.S -- vectors past 33 otherwise land in the default stub,
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* which reports 255. */
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#define SK_IPI_VECTOR 0x22
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/* Initialize Local APIC (enables APIC, sets spurious vector) */
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int apic_init(BootInfo *boot_info);
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/* Return this CPU's xAPIC ID (APIC_REG_ID bits 31:24) — used as the
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* destination field when programming I/O APIC redirection entries. */
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uint8_t apic_id(void);
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/* amd64 (FABRIC-3.10.8 MC-1a): send one IPI -- ICR high = destination,
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* then ICR low = `icr_low` -- and wait for its delivery status to clear.
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* Returns 0 once delivered, -1 if still pending after the bound. */
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int apic_send_ipi(uint8_t dest_apic_id, uint32_t icr_low);
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/* amd64 (MC-3b): on a secondary core, enable its own LAPIC (SIVR, TPR 0)
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* so it can take SK_IPI_VECTOR. Its timer LVT stays masked. */
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void apic_secondary_enable(void);
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/* Send End-of-Interrupt signal */
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void apic_eoi(void);
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/*
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* Initialize APIC timer for periodic heartbeat.
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* @param tsc_hz TSC frequency in Hz (for calibration)
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* @param tick_hz Desired tick frequency (e.g., 100 = 100 Hz = 10ms period)
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* @return 0 on success, -1 on failure
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*/
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int apic_timer_init(uint64_t tsc_hz, uint32_t tick_hz);
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/**
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* Start the APIC timer (enables periodic interrupts).
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* Call this after IDT and heartbeat handler are set up.
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*/
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void apic_timer_start(void);
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/**
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* Stop the APIC timer (disables periodic interrupts).
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*/
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void apic_timer_stop(void);
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/**
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* Re-arm the APIC timer at the current adaptive period (item 0.8, §26).
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* Recomputes the initial count from heartbeat_next_period_ns() and writes
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* it to the ICR; a periodic-mode ICR write restarts the countdown
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* immediately at the new value. Called once per tick from the ISR, before
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* heartbeat_tick().
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*/
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void apic_timer_rearm(void);
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/**
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* Get the configured timer period in TSC ticks.
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*/
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uint64_t apic_timer_period_tsc(void);
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#endif /* STARKERNEL_APIC_H */
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