FABRIC-3.10.0 ruled (multi-core now, ahead of O-D; row path A for O-D) and FABRIC-3.10.8 execution plan
- Captain Bob, 2026-09-25: "pin observr and dynmically utilize worker VM's"; MC-R1..R5 as proposed; MC-R6 changed to start now; O-D relaunches with row path A (serial-only DoE rows). The amd64 O-D launch was stopped after 81 min / 131,537 rows for this. - FABRIC-3.10.8: the traced inventory of shared state (kernel subsystems and the shared VM code -- notably one global dictionary lookup index for all VMs), and stages MC-0a..MC-4 with evidence named in advance. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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Robert Allan James
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Claude Opus 5.5
Claude Opus 5.5
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# FABRIC-3.10.0.md — Multi-core: observers pinned, workers claimed by the physics
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**Status: DESIGN, for Captain Bob's review. Nothing here authorizes an edit.** Proposed to start
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after O-D and the merge to `master` (ruling MC-R6). An execution plan (`FABRIC-3.10.8.md`) follows
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once the rulings are made. Part II (§8) records the OS's other open gaps as of this writing.
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**Status: RULED 2026-09-25 (§7); execution in `FABRIC-3.10.8.md`.** Multi-core starts now, ahead
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of O-D (MC-R6 as ruled). Part II (§8) records the OS's other open gaps as of this writing.
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**Provenance.** Opened 2026-09-25, while O-D (the DoE relaunch) was running on amd64. Captain Bob,
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2026-09-25:
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@@ -214,6 +213,17 @@ Each step keeps the system shippable and gets its own 3-ISA acceptance.
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5. **MC-R5: DoE core counts.** Which counts per ISA (proposed: 1, 2, 4).
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6. **MC-R6: timing.** Start after O-D and the merge (proposed).
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**RULED 2026-09-25, Captain Bob.** First, redirecting from the DoE row-path question: *"pin
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observr and dynmically utilize worker VM's."* Then, confirming:
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- MC-R1 to MC-R5 go **as proposed**: all three observers on core 0; one lock per subsystem, with
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Stadium's dispatch path partitioned; the last-core tie-break; count-based evidence; DoE at 1, 2
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and 4 cores.
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- **MC-R6 is changed:** multi-core starts **now, ahead of O-D**. O-D waits until it lands.
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- For O-D's relaunch, the row path is **A**: DoE rows go to serial only, skipping the
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framebuffer, whose full-screen scroll on every row was the rows-on bottleneck. The 2026-09-25
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amd64 launch (`logs/20260925-112529/amd64/`) was stopped for this after 81 minutes and 131,537
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rows, with no trial yet complete.
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---
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## 8. Part II — the OS's other open gaps (2026-09-25)
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@@ -0,0 +1,77 @@
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# FABRIC-3.10.8.md — Multi-core: execution plan and log
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**Status: IN PROGRESS.** Design and rulings are in `FABRIC-3.10.0.md` (ruled 2026-09-25, §7).
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Multi-core runs ahead of O-D (MC-R6 as ruled); O-D relaunches afterwards with row path A.
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Each stage:
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- needs Captain Bob's explicit go;
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- gets its own commit;
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- gets its own three-architecture acceptance (`clean qemu`; amd64, then aarch64, then riscv64;
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foreground; visible framebuffer; one at a time; coupled images reset before each).
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Evidence is named **before** each stage runs.
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**The standing acceptance sequence**, unchanged from `FABRIC-3.9.8.md`:
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- a boot to `[zuse@Hera] ok>` with zero `UNKNOWN WORD`, faults and frame corruption;
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- the `dict_hash` set identical across ISAs;
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- the Stage G interleave (A/B), byte-identical across ISAs while there is one worker core; by
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counts (A = 40, B = 40) once there are more (MC-R4);
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- the O-A checks (observer precedence, console responsive under load);
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- mint → WIREBIND → `USE` → `1 2 + .` → `3`;
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- 0 bytes of idle log growth over 20 s.
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**Never `make clean` an ISA while its QEMU runs:** it deletes that QEMU's QMP and serial
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sockets (found 2026-09-25).
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## 1. What MC-0 must cover (traced 2026-09-25)
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Everything that would break if two cores ran kernel or VM code at the same moment.
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**Kernel subsystems** (`src/starkernel/`), one lock each (MC-R2), except where noted:
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| Subsystem | Shared state | Treatment |
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|---|---|---|
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| `kmalloc`, `pmm`, `vmm` | free lists, bitmaps, page tables | heap lock; PMM lock; VMM lock |
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| kernel-Hermes | arena directory and segments, queue table, channel table, ledger, event counters | one lock |
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| Stadium | reservoirs, cells, quotas, word rows | **per-dispatch path partitioned by quota slot** (a VM's own row and cells need no lock while it runs on its one core); reservoir arithmetic atomic; cross-slot operations (admission evicting another VM's cell, grants, audits) take the Stadium lock |
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| VM registry, birth, kill, reap | registry list, names | registry lock; `KILL` refuses a VM running on another core |
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| switch-signal table | slots, stamps, decision-due flag | compare-and-swap for claim/release (MC-3); lock for register/unregister |
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| current VM, frame stack | `g_switch_current_vm` and friends | move to the per-core block |
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| console | UART, framebuffer VT100 state, line prefix state | one line lock |
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| log region, DoE region, block subsystem | rings, block chain, caches | a lock each |
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| heartbeat | tick counters | per-core counters (MC-3); one core until then |
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**Shared VM code** (`src/`, vendored; runs inside every VM):
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| File | Global | Treatment |
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|---|---|---|
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| `dictionary_management.c` | `sf_fc_list`/`sf_fc_count`/`sf_fc_cap`/`sf_cached_latest`: **one dictionary lookup index for all VMs**, rebuilt whenever a different VM's dictionary is searched | move into `VM` (per-VM index). Also stops the rebuild thrash on every switch today. |
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| `word_source/starforth_words.c` | `g_prng_state`: one PRNG stream for all VMs (accepted at Stage H) | an atomic step, so the stream stays one stream (order is nondeterministic across cores anyway, MC-R4) |
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| `physics_runtime.c` | `g_runtime` | inventory in MC-0; per-VM or atomic |
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| `word_source/dictionary_manipulation_words.c` | `state_variable` (STATE) | inventory in MC-0; per-VM |
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| `physics_hotwords_cache.c` | `g_hotwords_cache` | retired under `__STARKERNEL__` (item 4.1); confirm unused |
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| `word_source/ttf_words.c` | font and raster cache | core 0 only (Hestia's framebuffer) |
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## 2. Staged plan
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| Stage | Change | Evidence (named in advance) |
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|---|---|---|
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| **MC-0a** | **The per-core block, on one core.** A per-core structure reached through each ISA's per-CPU register (GS base / `TPIDR_EL1` / `tp`), set up for core 0 at boot. `g_switch_current_vm` moves into it. | Standard sequence unchanged. A probe reads the per-core pointer from a normal kernel path and from an interrupt handler, and gets core 0's block both times on all three ISAs. |
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| **MC-0b** | **Real spinlocks.** A kernel spinlock primitive (atomic exchange, interrupts masked while held on the owning core). `sf_mutex_*` stop being no-ops. The §1 kernel locks are added. | Standard sequence unchanged. A probe counts every lock's acquisitions and releases through a boot and the standard sequence: counts balance, and no lock is held across a context switch or on return to the idle point. |
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| **MC-0c** | **Shared VM code made per-VM or atomic** (§1, second table). The dictionary lookup index moves into `VM`. | The `dict_hash` set unchanged (the index is not hashed). A probe: two VMs searched alternately never rebuild each other's index. Standard sequence. |
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| **MC-0d** | **Stadium's dispatch path partitioned** (§1). | Standard sequence; conservation holds (`stadium_conserved()` on every VM, the ledger audit). A probe proves the dispatch path takes no shared lock. |
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| **MC-1** | **Bring up the extra cores and park them halted**, per ISA: amd64 (MADT, INIT-SIPI-SIPI, a position-independent trampoline below 1 MiB), aarch64 (DTB `/cpus`, PSCI `CPU_ON`), riscv64 (DTB harts, SBI HSM `hart_start`). QEMU gets `-smp 2`. | The boot reports each core online with its own per-core block; the extra cores sit halted (0 idle growth, no spin); the standard sequence unchanged. |
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| **MC-2** | **Observers get core-0 affinity.** | With one worker core, behaviour identical to today. A probe shows no observer ever claimed off core 0. |
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| **MC-3** | **Worker cores claim through the shared decision:** `running_on` with compare-and-swap, per-core idle contexts, per-core beats, wake by inter-processor interrupt. | Two workers genuinely overlapping in time on two cores. A probe counts double claims: 0. Conservation holds. G by counts. Idle worker cores halted (0 idle growth). |
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| **MC-4** | **DoE with cores as a factor** (after O-D): per-ISA campaigns at 1, 2 and 4 cores (MC-R5). | Per ISA and core count: 18 `MU-TRIAL` markers, `fail=0`, `MU-CAMPAIGN: complete`. |
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**Stop conditions** (re-plan rather than push on):
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- `dict_hash` diverges across ISAs;
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- conservation goes false;
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- a lock held across a switch, or an unbalanced lock count;
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- a double claim;
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- an idle core spinning.
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## 3. Execution log
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*(none yet)*
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