FABRIC-3.10.8 MC-1b: aarch64's second core online and parked

Cores from the DTB /cpus or, on QEMU (ACPI, no DTB), the MADT GICC entries; the MADT lookup is now shared (hal/acpi.c) with amd64. PSCI CPU_ON through the discovered conduit into ap_entry.S, which copies the boot core's MMU/control state, sets TPIDR_EL1 and parks. Core 1 online at EL1 with its own block; its vCPU thread 0.0% on the host. QEMU aarch64 -smp 2 -name debug-threads=on. 3-ISA acceptance clean. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
2026-09-26 13:16:33 -04:00
parent 24bde47481
commit 3a2ba5149f
16 changed files with 27949 additions and 48 deletions
@@ -0,0 +1,70 @@
+/*
+ * ap_entry.S (aarch64) -- secondary-core entry, FABRIC-3.10.8 MC-1b.
+ *
+ * PSCI CPU_ON lands here at EL1 with the MMU and caches off and
+ * x0 = the core's boot block (arch/aarch64/smp.c: a64_boot_t; the kernel
+ * is identity-mapped, so its address is physical too). The boot core has
+ * cleaned the block to the point of coherency, since these first loads
+ * bypass the caches.
+ *
+ * The core takes the boot core's own translation and control state --
+ * MAIR, TCR, TTBR0/1, VBAR, CPACR (FP/SIMD: kernel C uses it) -- then
+ * SCTLR, which turns the MMU and caches on at this same, identity-mapped
+ * address. It sets TPIDR_EL1 to its per-core block before any C code,
+ * records CurrentEL, and calls sk_smp_secondary_main(block) on its own
+ * stack. No symbol is referenced: every address comes from the block
+ * (this file is also assembled for the PE/COFF loader).
+ */
+
+    .section .text
+    .balign 4
+
+    .equ B_MAIR,    0
+    .equ B_TCR,     8
+    .equ B_TTBR0,   16
+    .equ B_TTBR1,   24
+    .equ B_VBAR,    32
+    .equ B_CPACR,   40
+    .equ B_SCTLR,   48
+    .equ B_PERCPU,  56
+    .equ B_STACK,   64
+    .equ B_ENTRY,   72
+    .equ B_EL,      80
+
+    .global sk_ap_entry_a64
+sk_ap_entry_a64:
+    msr   daifset, #0xf
+    mov   x19, x0
+    ldr   x1, [x19, #B_MAIR]
+    msr   mair_el1, x1
+    ldr   x1, [x19, #B_TCR]
+    msr   tcr_el1, x1
+    ldr   x1, [x19, #B_TTBR0]
+    msr   ttbr0_el1, x1
+    ldr   x1, [x19, #B_TTBR1]
+    msr   ttbr1_el1, x1
+    ldr   x1, [x19, #B_VBAR]
+    msr   vbar_el1, x1
+    ldr   x1, [x19, #B_CPACR]
+    msr   cpacr_el1, x1
+    isb
+    tlbi  vmalle1
+    dsb   nsh
+    ic    iallu
+    dsb   nsh
+    isb
+    ldr   x1, [x19, #B_SCTLR]
+    msr   sctlr_el1, x1
+    isb
+    ldr   x1, [x19, #B_PERCPU]
+    msr   tpidr_el1, x1
+    ldr   x1, [x19, #B_STACK]
+    mov   sp, x1
+    mrs   x2, CurrentEL
+    str   x2, [x19, #B_EL]
+    ldr   x3, [x19, #B_ENTRY]
+    ldr   x0, [x19, #B_PERCPU]
+    blr   x3
+1:
+    wfi
+    b     1b