FABRIC-3.10.8 MC-1b: aarch64's second core online and parked
Cores from the DTB /cpus or, on QEMU (ACPI, no DTB), the MADT GICC entries; the MADT lookup is now shared (hal/acpi.c) with amd64. PSCI CPU_ON through the discovered conduit into ap_entry.S, which copies the boot core's MMU/control state, sets TPIDR_EL1 and parks. Core 1 online at EL1 with its own block; its vCPU thread 0.0% on the host. QEMU aarch64 -smp 2 -name debug-threads=on. 3-ISA acceptance clean. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
This commit is contained in:
Robert Allan James
co-authored by
Claude Opus 5.5
Claude Opus 5.5
parent
24bde47481
commit
3a2ba5149f
@@ -0,0 +1,70 @@
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/*
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* ap_entry.S (aarch64) -- secondary-core entry, FABRIC-3.10.8 MC-1b.
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*
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* PSCI CPU_ON lands here at EL1 with the MMU and caches off and
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* x0 = the core's boot block (arch/aarch64/smp.c: a64_boot_t; the kernel
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* is identity-mapped, so its address is physical too). The boot core has
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* cleaned the block to the point of coherency, since these first loads
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* bypass the caches.
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*
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* The core takes the boot core's own translation and control state --
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* MAIR, TCR, TTBR0/1, VBAR, CPACR (FP/SIMD: kernel C uses it) -- then
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* SCTLR, which turns the MMU and caches on at this same, identity-mapped
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* address. It sets TPIDR_EL1 to its per-core block before any C code,
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* records CurrentEL, and calls sk_smp_secondary_main(block) on its own
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* stack. No symbol is referenced: every address comes from the block
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* (this file is also assembled for the PE/COFF loader).
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*/
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.section .text
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.balign 4
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.equ B_MAIR, 0
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.equ B_TCR, 8
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.equ B_TTBR0, 16
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.equ B_TTBR1, 24
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.equ B_VBAR, 32
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.equ B_CPACR, 40
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.equ B_SCTLR, 48
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.equ B_PERCPU, 56
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.equ B_STACK, 64
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.equ B_ENTRY, 72
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.equ B_EL, 80
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.global sk_ap_entry_a64
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sk_ap_entry_a64:
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msr daifset, #0xf
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mov x19, x0
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ldr x1, [x19, #B_MAIR]
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msr mair_el1, x1
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ldr x1, [x19, #B_TCR]
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msr tcr_el1, x1
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ldr x1, [x19, #B_TTBR0]
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msr ttbr0_el1, x1
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ldr x1, [x19, #B_TTBR1]
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msr ttbr1_el1, x1
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ldr x1, [x19, #B_VBAR]
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msr vbar_el1, x1
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ldr x1, [x19, #B_CPACR]
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msr cpacr_el1, x1
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isb
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tlbi vmalle1
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dsb nsh
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ic iallu
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dsb nsh
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isb
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ldr x1, [x19, #B_SCTLR]
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msr sctlr_el1, x1
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isb
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ldr x1, [x19, #B_PERCPU]
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msr tpidr_el1, x1
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ldr x1, [x19, #B_STACK]
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mov sp, x1
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mrs x2, CurrentEL
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str x2, [x19, #B_EL]
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ldr x3, [x19, #B_ENTRY]
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ldr x0, [x19, #B_PERCPU]
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blr x3
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1:
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wfi
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b 1b
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@@ -192,6 +192,27 @@ void aarch64_psci_conduit_init(const void *dtb)
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}
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}
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/**
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* @brief PSCI CPU_ON (SMC64, 0xC4000003) through the discovered conduit.
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*
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* FABRIC-3.10.8 MC-1b: starts core @p mpidr at physical @p entry with
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* x0 = @p context_id. Returns PSCI's status (0 = SUCCESS, -4 ALREADY_ON,
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* -2 INVALID_PARAMETERS, ...).
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*/
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int64_t aarch64_psci_cpu_on(uint64_t mpidr, uint64_t entry, uint64_t context_id)
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{
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register uint64_t x0 __asm__("x0") = 0xC4000003ull;
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register uint64_t x1 __asm__("x1") = mpidr;
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register uint64_t x2 __asm__("x2") = entry;
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register uint64_t x3 __asm__("x3") = context_id;
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if (s_psci_use_smc) {
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__asm__ volatile ("smc #0" : "+r"(x0), "+r"(x1), "+r"(x2), "+r"(x3) :: "memory");
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} else {
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__asm__ volatile ("hvc #0" : "+r"(x0), "+r"(x1), "+r"(x2), "+r"(x3) :: "memory");
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}
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return (int64_t)x0;
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}
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void arch_cold_reset(void)
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{
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arch_disable_interrupts();
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@@ -0,0 +1,208 @@
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/*
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StarForth — Steady-State Virtual Machine Runtime
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Copyright (c) 2023–2025 Robert A. James
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All rights reserved.
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This file is part of the StarForth project.
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Licensed under the StarForth License, Version 1.0 (the "License");
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you may not use this file except in compliance with the License.
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*/
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/**
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* smp.c (aarch64) - secondary-core bring-up, FABRIC-3.10.8 MC-1b.
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*
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* Cores come from the devicetree's /cpus when the firmware hands one over
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* (the Raspberry Pi 5), otherwise from the ACPI MADT's GICC entries (QEMU's
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* AAVMF hands over ACPI and no DTB). The hardware id is the MPIDR affinity
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* (Aff3..Aff0). Each core is started with PSCI CPU_ON through the conduit
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* arch.c discovered, into ap_entry.S, with x0 = its boot block.
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*/
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#include "starkernel/smp.h"
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#include "starkernel/acpi.h"
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#include "starkernel/fdt.h"
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#include "starkernel/kmalloc.h"
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#include "starkernel/console.h"
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#include "freestanding/stdio.h"
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#include "uefi.h"
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extern void sk_ap_entry_a64(void);
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extern int64_t aarch64_psci_cpu_on(uint64_t mpidr, uint64_t entry, uint64_t context_id);
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#define MPIDR_AFF_MASK 0xFF00FFFFFFull /* Aff3 [39:32], Aff2..Aff0 [23:0] */
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/* The core's boot block (ap_entry.S, B_* offsets). Heap-allocated per core
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* and kept: the core reads it with its MMU off, then writes B_EL. */
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typedef struct {
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uint64_t mair, tcr, ttbr0, ttbr1, vbar, cpacr, sctlr;
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uint64_t percpu, stack, entry;
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volatile uint64_t el;
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} a64_boot_t;
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static uint64_t be_cells(const uint8_t *p, uint32_t cells)
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{
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uint64_t v = 0;
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uint32_t i;
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for (i = 0; i < cells * 4u; i++) v = (v << 8) | p[i];
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return v;
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}
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static int id_seen(const uint64_t *ids, uint32_t n, uint64_t id)
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{
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uint32_t i;
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for (i = 0; i < n; i++) if (ids[i] == id) return 1;
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return 0;
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}
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static void add_id(uint64_t *ids, uint32_t cap, uint32_t *n, uint64_t id)
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{
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if (cap) {
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if (id_seen(ids, *n < cap ? *n : cap, id)) return;
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if (*n < cap) ids[*n] = id;
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}
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(*n)++;
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}
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static uint32_t enumerate_dtb(const void *dtb, uint64_t *ids, uint32_t cap)
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{
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const void *cpus = fdt_find_node_by_name(dtb, "cpus");
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const void *c = (const void *)0;
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const uint8_t *ac;
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uint32_t len, cells = 1, n = 0;
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if (!cpus) return 0;
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ac = (const uint8_t *)fdt_find_prop_in_node(dtb, cpus, "#address-cells", &len);
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if (ac && len == 4) cells = (uint32_t)be_cells(ac, 1);
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if (cells < 1 || cells > 2) cells = 1;
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while ((c = fdt_next_child_node(dtb, cpus, c)) != (const void *)0) {
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const char *type = (const char *)fdt_find_prop_in_node(dtb, c, "device_type", &len);
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const uint8_t *reg;
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if (!type || len < 4 || type[0] != 'c' || type[1] != 'p' || type[2] != 'u' || type[3] != 0) continue;
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reg = (const uint8_t *)fdt_find_prop_in_node(dtb, c, "reg", &len);
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if (!reg || len < cells * 4u) continue;
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add_id(ids, cap, &n, be_cells(reg, cells) & MPIDR_AFF_MASK);
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}
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return n;
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}
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/* MADT type 0x0B (GICC): flags at +12 (bit 0 enabled), MPIDR at +68. */
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static uint32_t enumerate_madt(const void *rsdp, uint64_t *ids, uint32_t cap)
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{
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const uint8_t *madt = acpi_find_table(rsdp, "APIC");
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const uint8_t *p, *end;
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uint32_t n = 0;
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if (!madt) return 0;
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end = madt + acpi_table_length(madt);
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for (p = madt + 44; p + 2 <= end; p += p[1]) {
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uint32_t flags;
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uint64_t mpidr;
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uint32_t k;
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if (p[1] == 0 || p + p[1] > end) break;
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if (p[0] != 0x0B || p[1] < 76) continue;
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flags = (uint32_t)p[12] | ((uint32_t)p[13] << 8) | ((uint32_t)p[14] << 16) | ((uint32_t)p[15] << 24);
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if (!(flags & 1u)) continue;
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mpidr = 0;
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for (k = 0; k < 8; k++) mpidr |= (uint64_t)p[68 + k] << (8 * k);
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add_id(ids, cap, &n, mpidr & MPIDR_AFF_MASK);
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}
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return n;
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}
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uint64_t arch_smp_boot_hw_id(void)
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{
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uint64_t m;
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__asm__ volatile ("mrs %0, mpidr_el1" : "=r"(m));
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return m & MPIDR_AFF_MASK;
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}
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uint32_t arch_smp_enumerate(BootInfo *boot_info, uint64_t *hw_ids, uint32_t cap)
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{
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uint32_t n = 0;
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if (boot_info && fdt_valid(boot_info->dtb)) n = enumerate_dtb(boot_info->dtb, hw_ids, cap);
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if (n == 0 && boot_info) n = enumerate_madt(boot_info->acpi_table, hw_ids, cap);
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if (n == 0) {
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if (cap) hw_ids[0] = arch_smp_boot_hw_id();
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return 1;
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}
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return n;
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}
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void arch_smp_park_once(void)
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{
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__asm__ volatile ("msr daifset, #0xf\n\twfi" ::: "memory");
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}
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/* Clean [p, p+len) to the point of coherency: the core reads it with its
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* MMU and caches off. */
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static void clean_to_poc(const void *p, uint64_t len)
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{
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uint64_t a = (uint64_t)(uintptr_t)p & ~63ull, end = (uint64_t)(uintptr_t)p + len;
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for (; a < end; a += 64) __asm__ volatile ("dc cvac, %0" :: "r"(a) : "memory");
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__asm__ volatile ("dsb sy" ::: "memory");
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}
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/* Each started core's block, found again by arch_smp_arrival(): keyed by
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* the per-core block, so a list (heap), not a table. */
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typedef struct a64_started { sk_percpu_t *pc; a64_boot_t *b; struct a64_started *next; } a64_started_t;
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static a64_started_t *g_started;
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int arch_smp_start(BootInfo *boot_info, sk_percpu_t *pc, void *stack_top)
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{
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a64_boot_t *b;
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a64_started_t *s;
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int64_t rc;
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uint64_t v;
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(void)boot_info;
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b = (a64_boot_t *)kmalloc(sizeof(a64_boot_t));
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s = (a64_started_t *)kmalloc(sizeof(a64_started_t));
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if (!b || !s) {
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if (b) kfree(b);
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if (s) kfree(s);
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return -1;
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}
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__asm__ volatile ("mrs %0, mair_el1" : "=r"(v)); b->mair = v;
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__asm__ volatile ("mrs %0, tcr_el1" : "=r"(v)); b->tcr = v;
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__asm__ volatile ("mrs %0, ttbr0_el1" : "=r"(v)); b->ttbr0 = v;
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__asm__ volatile ("mrs %0, ttbr1_el1" : "=r"(v)); b->ttbr1 = v;
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__asm__ volatile ("mrs %0, vbar_el1" : "=r"(v)); b->vbar = v;
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__asm__ volatile ("mrs %0, cpacr_el1" : "=r"(v)); b->cpacr = v;
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__asm__ volatile ("mrs %0, sctlr_el1" : "=r"(v)); b->sctlr = v;
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b->percpu = (uint64_t)(uintptr_t)pc;
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b->stack = (uint64_t)(uintptr_t)stack_top & ~15ull;
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b->entry = (uint64_t)(uintptr_t)&sk_smp_secondary_main;
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b->el = 0;
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s->pc = pc; s->b = b; s->next = g_started; g_started = s;
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clean_to_poc(b, sizeof(*b));
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clean_to_poc(pc, sizeof(*pc));
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clean_to_poc((const void *)&sk_ap_entry_a64, 256);
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rc = aarch64_psci_cpu_on(pc->hw_id, (uint64_t)(uintptr_t)&sk_ap_entry_a64, (uint64_t)(uintptr_t)b);
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if (rc != 0) {
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char line[96];
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snprintf(line, sizeof line, "SMP: PSCI CPU_ON returned %lld", (long long)rc);
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console_println(line);
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return -1;
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}
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return 0;
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}
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const char *arch_smp_arrival(const sk_percpu_t *pc)
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{
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a64_started_t *s;
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for (s = g_started; s; s = s->next) {
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if (s->pc == pc) {
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switch ((s->b->el >> 2) & 3u) {
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case 1: return "EL1";
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case 2: return "EL2";
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case 3: return "EL3";
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default: return "EL0?";
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}
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}
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}
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return "?";
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}
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