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Verilator co-simulation of one node, and a per-instruction state trace from the golden model #8

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opened 2026-11-06 16:01:22 +00:00 by rajames · 0 comments
rajames commented 2026-11-06 16:01:22 +00:00
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JUSTIFICATION.md section 14. There is no node RTL in the tree yet. The golden model has no way to output its state after each instruction (stacks, registers, heat) for a lockstep comparison -- that part can be built now, before the RTL.

JUSTIFICATION.md section 14. There is no node RTL in the tree yet. The golden model has no way to output its state after each instruction (stacks, registers, heat) for a lockstep comparison -- that part can be built now, before the RTL.
rajames added this to the v4.0.0 milestone 2026-11-06 16:01:22 +00:00
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Reference: rajames/LithosAnanke#8