rajamesandClaude Opus 5.5
0e2c60dac3
boards/BRINGUP.md R2/R3, FABRIC-3 SXXXIX. The entry stub cleans the cache over the image, builds an identity map (the image's GiB Normal, the rest Device) and enables MMU and caches at EL2 (or EL1); rpi5_mmu.c makes the devicetree's RAM Normal and the framebuffer uncached. Mailbox waits give up after one second; the buffer is cleaned around the exchange; the framebuffer address goes through dma-ranges, not a Pi 4 mask. New rpi5-rehearsal target runs the native image on QEMU virt at EL2. It found three more that would each have stopped the board: the PL011 shift (mine, c9519173; the host test asserted it), the GIC address not carried through /soc's ranges (new fdt_reg_address(), checked against the real Pi 5 DTB), and no timer IRQ at EL2 (HCR_EL2.IMO/FMO/AMO). Rehearsal: POST 1052 passed, same parity hash as UEFI. Standard acceptance on three ISAs: POST 1052, hash 0x82f4ae7cb2e2d424. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
27 lines
827 B
C
27 lines
827 B
C
/*
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StarForth — Steady-State Virtual Machine Runtime
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Copyright (c) 2023–2026 Robert A. James. All rights reserved.
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Licensed under the StarForth License, Version 1.0.
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*/
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/**
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* rpi5_mmu.h - the Pi 5 native path's identity map, once C runs
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* (rpi5_mmu.c; native_rpi5_entry.S turns the MMU on).
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*/
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#ifndef STARKERNEL_RPI5_MMU_H
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#define STARKERNEL_RPI5_MMU_H
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#include <stdint.h>
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/* Makes every further GiB the devicetree's /memory covers entirely Normal
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* write-back. Returns how many GiB entries changed, or -1 if /memory
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* cannot be read. */
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int rpi5_mmu_map_ram(const void *dtb);
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/* Makes [addr, addr+size) Normal non-cacheable (2 MiB blocks in the first
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* GiB, a whole GiB above it). Returns 0, or -1 if it cannot. */
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int rpi5_mmu_uncached(uint64_t addr, uint64_t size);
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#endif /* STARKERNEL_RPI5_MMU_H */
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