Robert Allan JamesandClaude Opus 5.5
71e0be96b0
Each worker core sets up its own IPI receiver before going online (amd64 LAPIC + vector 0x22 with its own stub, aarch64 banked GIC SGI 0, riscv64 sie.SSIE); core 0 sends by ICR / GICD_SGIR / SBI IPI. Park lets exactly one interrupt in without a lost-wake window. Boot self-test: IPI round trips 3/3 and 'woke x3, IPIs x3' on all three ISAs; worker vCPU threads 0.0% on the host. 3-ISA acceptance clean. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
src/starkernel/arch/amd64/
AMD64 architecture support for LithosAnanke.
arch.c— architecture init entry point.apic.c— Local APIC interrupt controller driver.timer.c— TSC/HPET/APIC timer setup (100 Hz heartbeat tick).interrupts.c— IDT setup and interrupt dispatch.boot.S— early boot assembly.kernel_entry.S— kernel entry trampoline invoked from the loader.isr.S— interrupt service routine stubs.