rajamesandJunie
a8b70e88d3
Source tree reorganization: - Move StarForth v3 engine to v3/ (src/, include/, Makefile) - Move kernel to kernel/ (src/, include/, linker/, Makefile) - Create v4/ skeleton for F18-ISA golden model (DECOMPOSITION.md, JUSTIFICATION.md) - Move FABRIC-0..4.md to docs/fabric/ - Move ONTOLOGY.md and ROADMAP.md to docs/ Board infrastructure: - Add boards/ser5/, boards/raspi/, boards/milkv/, boards/zynq7020/ - Each board has board.mk (ISA, CPU flags, boot recipe) and README.md - Root Makefile becomes thin dispatcher: boot_image, all, clean, docs take TARGET - make boot_image TARGET=SER5|RASPI|MILKV builds one GPT/MBR image per board - ZYNQ7020 target exists but stops with clear error (ARMv7 port not built yet) - scripts/mkdiskimage.sh builds disk images for all boards Docs pipeline: - docs/book/ with LaTeX master (main.tex) and Makefile - pandoc converts Markdown to LaTeX at build time - Two Lua filters: table-widths.lua (wide tables wrap), code-breaks.lua (inline code breaks) - make docs builds single PDF (754 pages, 0 missing characters) - make docs TARGET=<board> adds board appendix - build/docs/<book|board>/meta.tex stamps git commit into PDF Bug fixes: - 42 include paths that only worked by accident now use correct relative paths - clang-18 hardcode replaced with configurable CC variable (fixed aarch64 build) - Pi 5: kernel_2712.img linked at 0x80000, .bss zeroed, memory reserved - Doxyfile, .clang-tidy, README.md, Kconfig paths updated Verified: - Hosted v3 build passes 1012 tests, 0 failures - SER5 image boots in QEMU (OVMF), POST passes, K exact (65536 = Q48_ONE) - Milk-V image boots in QEMU (OpenSBI + U-Boot + bootefi), POST passes - make clean TARGET=<board> removes only that board and its ISA objects - make all builds all boards, hosted v3, and docs in one run Co-authored-by: Junie <junie@jetbrains.com>
107 lines
3.3 KiB
C
107 lines
3.3 KiB
C
/*
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StarForth — Steady-State Virtual Machine Runtime
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Copyright (c) 2023–2025 Robert A. James
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All rights reserved.
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This file is part of the StarForth project.
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Licensed under the StarForth License, Version 1.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at:
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https://github.com/star.4th@proton.me/StarForth/LICENSE.txt
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This software is provided "AS IS", WITHOUT WARRANTY OF ANY KIND,
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express or implied, including but not limited to the warranties of
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merchantability, fitness for a particular purpose, and noninfringement.
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See the License for the specific language governing permissions and
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limitations under the License.
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StarForth — Steady-State Virtual Machine Runtime
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Copyright (c) 2023–2025 Robert A. James
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All rights reserved.
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This file is part of the StarForth project.
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Licensed under the StarForth License, Version 1.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at:
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https://github.com/star.4th@proton.me/StarForth/LICENSE.txt
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This software is provided "AS IS", WITHOUT WARRANTY OF ANY KIND,
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express or implied, including but not limited to the warranties of
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merchantability, fitness for a particular purpose, and noninfringement.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* apic.h - Local APIC interface
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*/
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#ifndef STARKERNEL_APIC_H
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#define STARKERNEL_APIC_H
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#include "uefi.h"
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#include <stdint.h>
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/* Heartbeat timer vector (user-defined IRQ space starts at 0x20) */
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#define APIC_TIMER_VECTOR 0x20
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/* Spurious-interrupt vector (APIC_REG_SIVR, set in apic_init()). A normal,
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* occasional hardware race per Intel SDM Vol.3 §10.9 -- not a fault. Must
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* be silently ignored with no EOI. Surfaced by item 4.3.5's I/O APIC work:
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* no real external interrupt had ever been delivered through the I/O APIC
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* before, so this path was previously dormant. */
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#define APIC_SPURIOUS_VECTOR 0xFF
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/* Initialize Local APIC (enables APIC, sets spurious vector) */
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int apic_init(BootInfo *boot_info);
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/* Return this CPU's xAPIC ID (APIC_REG_ID bits 31:24) — used as the
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* destination field when programming I/O APIC redirection entries. */
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uint8_t apic_id(void);
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/* Send End-of-Interrupt signal */
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void apic_eoi(void);
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/*
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* Initialize APIC timer for periodic heartbeat.
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* @param tsc_hz TSC frequency in Hz (for calibration)
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* @param tick_hz Desired tick frequency (e.g., 100 = 100 Hz = 10ms period)
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* @return 0 on success, -1 on failure
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*/
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int apic_timer_init(uint64_t tsc_hz, uint32_t tick_hz);
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/**
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* Start the APIC timer (enables periodic interrupts).
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* Call this after IDT and heartbeat handler are set up.
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*/
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void apic_timer_start(void);
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/**
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* Stop the APIC timer (disables periodic interrupts).
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*/
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void apic_timer_stop(void);
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/**
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* Re-arm the APIC timer at the current adaptive period (item 0.8, §26).
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* Recomputes the initial count from heartbeat_next_period_ns() and writes
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* it to the ICR; a periodic-mode ICR write restarts the countdown
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* immediately at the new value. Called once per tick from the ISR, before
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* heartbeat_tick().
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*/
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void apic_timer_rearm(void);
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/**
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* Get the configured timer period in TSC ticks.
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*/
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uint64_t apic_timer_period_tsc(void);
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#endif /* STARKERNEL_APIC_H */
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