Robert Allan JamesandClaude Opus 5.5
3a2ba5149f
Cores from the DTB /cpus or, on QEMU (ACPI, no DTB), the MADT GICC entries; the MADT lookup is now shared (hal/acpi.c) with amd64. PSCI CPU_ON through the discovered conduit into ap_entry.S, which copies the boot core's MMU/control state, sets TPIDR_EL1 and parks. Core 1 online at EL1 with its own block; its vCPU thread 0.0% on the host. QEMU aarch64 -smp 2 -name debug-threads=on. 3-ISA acceptance clean. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
src/starkernel/arch/amd64/
AMD64 architecture support for LithosAnanke.
arch.c— architecture init entry point.apic.c— Local APIC interrupt controller driver.timer.c— TSC/HPET/APIC timer setup (100 Hz heartbeat tick).interrupts.c— IDT setup and interrupt dispatch.boot.S— early boot assembly.kernel_entry.S— kernel entry trampoline invoked from the loader.isr.S— interrupt service routine stubs.