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Robert Allan JamesandClaude Sonnet 5 2a2d7c5e5e aarch64: GIC SPI wiring for virtio-input (item 4.3.5d)

Punch list §25 item 4.3.5d complete.

New apic_spi_enable(intid) generalizes item 0.6's PPI-only sequence to one
explicit SPI (IPRIORITYR/ISENABLER/ITARGETSR, ICFGR read-checked not
written). Verified via a software-pended SPI (GICD_ISPENDR, no device
needed) through the existing generic IRQ dispatch, which needed no changes.
Found and fixed a real bug during verification: PSTATE.I is still set at
apic_init()'s point in boot, so the first self-test run correctly latched
but never took the interrupt. Self-test code reverted after capturing
evidence -- interrupts.c has zero net diff, only apic_spi_enable() remains,
unused until 4.3.5e. Three-arch acceptance boot clean.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>

2026-08-08 12:15:23 -04:00

apic.c

aarch64: GIC SPI wiring for virtio-input (item 4.3.5d)

2026-08-08 12:15:23 -04:00

arch.c

aarch64: detect exception level at runtime, cached accessor

2026-08-03 18:30:25 -04:00

boot.S

Initial commit — LithosAnanke kernel

2026-08-01 07:49:56 -04:00

interrupts.c

aarch64: arm the ARM Generic Timer -- CNTP/CNTHP TVAL+CTL, per-tick re-arm

2026-08-03 22:14:52 -04:00

isr.S

aarch64: split irq_spx into a real save/dispatch/restore/ERET trampoline

2026-08-03 18:47:29 -04:00

README.md

Initial commit — LithosAnanke kernel

2026-08-01 07:49:56 -04:00

timer.c

starkernel: converge the tick path and wire the adaptive heartbeat (item 0.8)

2026-08-04 00:01:48 -04:00

README.md

src/starkernel/arch/aarch64/

AArch64 architecture support for LithosAnanke.

arch.c — architecture init entry point.
apic.c — GIC (Generic Interrupt Controller) stub, named apic.c to match the shared per-arch file-naming convention across amd64/aarch64/riscv64. Satisfies the common apic_init()/apic_eoi() call sites without real GIC bring-up yet; deferred to a later milestone.
timer.c — architected timer setup (heartbeat tick source).
interrupts.c — exception vector table setup and interrupt dispatch.
boot.S — early boot assembly.
isr.S — interrupt service routine stubs.

No kernel_entry.S — aarch64 uses a different UEFI loader entry path (clang/lld-link COFF target, since GCC cannot produce an aarch64 PE image; see Makefile.starkernel).