hal/smp.c: dense logical core ids, a heap-sized core table, one-at-a-time bring-up under a 1 s bound, park-wake reporting at the idle point. amd64: MADT enumeration, a relocation-free real->long-mode trampoline copied below 1 MiB, INIT-SIPI-SIPI via the LAPIC ICR; QEMU -smp 2. Core 1 reports online with GS on its own block, parks with 0 wakes; aarch64/riscv64 report 1 core until MC-1b/c. 3-ISA acceptance clean. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
src/starkernel/arch/amd64/
AMD64 architecture support for LithosAnanke.
arch.c— architecture init entry point.apic.c— Local APIC interrupt controller driver.timer.c— TSC/HPET/APIC timer setup (100 Hz heartbeat tick).interrupts.c— IDT setup and interrupt dispatch.boot.S— early boot assembly.kernel_entry.S— kernel entry trampoline invoked from the loader.isr.S— interrupt service routine stubs.