hal/smp.c: dense logical core ids, a heap-sized core table, one-at-a-time bring-up under a 1 s bound, park-wake reporting at the idle point. amd64: MADT enumeration, a relocation-free real->long-mode trampoline copied below 1 MiB, INIT-SIPI-SIPI via the LAPIC ICR; QEMU -smp 2. Core 1 reports online with GS on its own block, parks with 0 wakes; aarch64/riscv64 report 1 core until MC-1b/c. 3-ISA acceptance clean. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
112 lines
3.6 KiB
C
112 lines
3.6 KiB
C
/*
|
||
StarForth — Steady-State Virtual Machine Runtime
|
||
|
||
Copyright (c) 2023–2025 Robert A. James
|
||
All rights reserved.
|
||
|
||
This file is part of the StarForth project.
|
||
|
||
Licensed under the StarForth License, Version 1.0 (the "License");
|
||
you may not use this file except in compliance with the License.
|
||
|
||
You may obtain a copy of the License at:
|
||
https://github.com/star.4th@proton.me/StarForth/LICENSE.txt
|
||
|
||
This software is provided "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||
express or implied, including but not limited to the warranties of
|
||
merchantability, fitness for a particular purpose, and noninfringement.
|
||
|
||
See the License for the specific language governing permissions and
|
||
limitations under the License.
|
||
|
||
StarForth — Steady-State Virtual Machine Runtime
|
||
Copyright (c) 2023–2025 Robert A. James
|
||
All rights reserved.
|
||
|
||
This file is part of the StarForth project.
|
||
|
||
Licensed under the StarForth License, Version 1.0 (the "License");
|
||
you may not use this file except in compliance with the License.
|
||
|
||
You may obtain a copy of the License at:
|
||
https://github.com/star.4th@proton.me/StarForth/LICENSE.txt
|
||
|
||
This software is provided "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||
express or implied, including but not limited to the warranties of
|
||
merchantability, fitness for a particular purpose, and noninfringement.
|
||
|
||
See the License for the specific language governing permissions and
|
||
limitations under the License.
|
||
|
||
*/
|
||
|
||
/**
|
||
* apic.h - Local APIC interface
|
||
*/
|
||
|
||
#ifndef STARKERNEL_APIC_H
|
||
#define STARKERNEL_APIC_H
|
||
|
||
#include "uefi.h"
|
||
#include <stdint.h>
|
||
|
||
/* Heartbeat timer vector (user-defined IRQ space starts at 0x20) */
|
||
#define APIC_TIMER_VECTOR 0x20
|
||
|
||
/* Spurious-interrupt vector (APIC_REG_SIVR, set in apic_init()). A normal,
|
||
* occasional hardware race per Intel SDM Vol.3 §10.9 -- not a fault. Must
|
||
* be silently ignored with no EOI. Surfaced by item 4.3.5's I/O APIC work:
|
||
* no real external interrupt had ever been delivered through the I/O APIC
|
||
* before, so this path was previously dormant. */
|
||
#define APIC_SPURIOUS_VECTOR 0xFF
|
||
|
||
/* Initialize Local APIC (enables APIC, sets spurious vector) */
|
||
int apic_init(BootInfo *boot_info);
|
||
|
||
/* Return this CPU's xAPIC ID (APIC_REG_ID bits 31:24) — used as the
|
||
* destination field when programming I/O APIC redirection entries. */
|
||
uint8_t apic_id(void);
|
||
|
||
/* amd64 (FABRIC-3.10.8 MC-1a): send one IPI -- ICR high = destination,
|
||
* then ICR low = `icr_low` -- and wait for its delivery status to clear.
|
||
* Returns 0 once delivered, -1 if still pending after the bound. */
|
||
int apic_send_ipi(uint8_t dest_apic_id, uint32_t icr_low);
|
||
|
||
/* Send End-of-Interrupt signal */
|
||
void apic_eoi(void);
|
||
|
||
/*
|
||
* Initialize APIC timer for periodic heartbeat.
|
||
* @param tsc_hz TSC frequency in Hz (for calibration)
|
||
* @param tick_hz Desired tick frequency (e.g., 100 = 100 Hz = 10ms period)
|
||
* @return 0 on success, -1 on failure
|
||
*/
|
||
int apic_timer_init(uint64_t tsc_hz, uint32_t tick_hz);
|
||
|
||
/**
|
||
* Start the APIC timer (enables periodic interrupts).
|
||
* Call this after IDT and heartbeat handler are set up.
|
||
*/
|
||
void apic_timer_start(void);
|
||
|
||
/**
|
||
* Stop the APIC timer (disables periodic interrupts).
|
||
*/
|
||
void apic_timer_stop(void);
|
||
|
||
/**
|
||
* Re-arm the APIC timer at the current adaptive period (item 0.8, §26).
|
||
* Recomputes the initial count from heartbeat_next_period_ns() and writes
|
||
* it to the ICR; a periodic-mode ICR write restarts the countdown
|
||
* immediately at the new value. Called once per tick from the ISR, before
|
||
* heartbeat_tick().
|
||
*/
|
||
void apic_timer_rearm(void);
|
||
|
||
/**
|
||
* Get the configured timer period in TSC ticks.
|
||
*/
|
||
uint64_t apic_timer_period_tsc(void);
|
||
|
||
#endif /* STARKERNEL_APIC_H */
|