Stage 2: cooperative VM context switch primitive, proven on all 3 arches (FABRIC-3.md §XXVIII)

Third stage of the preemptive context-switching plan. The real
save/restore switch mechanism now exists -- the first time anything has
ever executed on a VM's own native stack (Stage 1 allocated them,
unused).

New sk_vm_switch_to() (switch.S, one per arch) is an ordinary function
call, not an interrupt -- so unlike Stage 0's trap frame, the ABI already
covers every caller-saved register; only the callee-saved set needs
explicit save/restore (amd64: rbx/rbp/r12-r15, no FP at all since SysV
has no callee-saved XMM; aarch64: x19-x28/x29/x30 + d8-d15; riscv64:
s0-s11/ra + fs0-fs11, FS-gated like Stage 0 but read once and reused for
both halves within one call, since FS is genuine global CPU state, not
part of what's switched). A sibling sk_vm_switch_prime() in the same file
builds the synthetic first-entry frame, kept in assembly so the layout
can never drift out of sync with sk_vm_switch_to() itself.

New switch.c/switch.h: sk_vm_context_switch(from, to) handles first-entry
priming vs. resuming a parked context, and updates registry state (new
VM_STATE_SWITCHED_OUT, distinct from VM_STATE_STOPPED -- STOPPED means no
live frame, this means the opposite). sk_vm_switch_entry() is the minimal
permanent trampoline every freshly-entered VM lands in: no production
behavior defined yet, so it just yields straight back to whoever switched
to it, forever.

Closes the confirmed unguarded-KILL UAF found during planning:
capsule_vm_kill(), mama_word_kill(), and capsule_vm_kill_all_nonmama()
all now refuse (or silently leak rather than free, on the cold-restart
path where arch_cold_reset() wipes everything immediately after anyway)
tearing down a switched-out VM. Side effect found, not built on purpose:
the existing MSG-TICK idle-pump already filters on VM_STATE_LIVE, so it
automatically stopped dispatching into a switched-out VM with zero
changes needed there.

Verified via a temporary SWITCH-TEST probe (boot-triggered, since nothing
can type interactively into a foreground-only QEMU session) that
round-tripped a sentinel through 5 real Hera<->Hermes switches on all 3
architectures: 5/5 rounds, 0 failures, clean continuation to ok>. Probe
fully reverted after capture; kernel_main.c shows zero diff.

Also: Makefile.starkernel's LOADER_EXTRA_SRCS/LOADER_ASM needed the new
files added explicitly (this project's "loader" PE binary is the full
running kernel, not a thin bootstrap stage), and aarch64's switch.S
needed the same #ifndef _WIN32 guard around .hidden that isr.S already
carries (aarch64's loader assembles via clang targeting a PE/COFF
target with no .hidden equivalent) -- caught by a build failure, fixed.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_016UNhH1mhi52i6Qihh7ZV5S

src/starkernel/arch/amd64/switch.S

@@ -0,0 +1,79 @@
+/*
+ * switch.S (amd64) - Cooperative VM context switch primitive.
+ *
+ * FABRIC-3.md §XXVIII (Stage 2, preemptive-context-switch save/restore
+ * primitive, 2026-09-13). This is deliberately NOT the same mechanism as
+ * isr.S's interrupt trap frame (Stage 0) -- that saves every register
+ * because an interrupt is not a call site the interrupted code knows
+ * about. sk_vm_switch_to() IS an ordinary function call (SWITCH-TO's C
+ * handler calls it directly), so the standard System V AMD64 ABI already
+ * guarantees every caller-saved register (rax, rcx, rdx, rsi, rdi, r8-r11,
+ * all XMM) is the caller's own problem to preserve across the call, exactly
+ * like any other call. Only the callee-saved set -- rbx, rbp, r12-r15 --
+ * needs explicit handling here, because this function does not really
+ * "return" in the normal sense: it swaps to a completely different stack
+ * and (from the newly-resumed context's point of view) appears to return
+ * from whichever earlier call to this same function originally parked it.
+ * SysV has no callee-saved XMM registers at all, so there is no FP state
+ * to carry here.
+ *
+ * void sk_vm_switch_to(uint64_t *save_sp_out, uint64_t new_sp);
+ *   rdi = save_sp_out, rsi = new_sp
+ *
+ * For a VM that has never run before, new_sp must point at a synthetic
+ * frame built to this exact layout by the C glue (switch.c): six zeroed
+ * quadwords (r15, r14, r13, r12, rbx, rbp -- values irrelevant, never a
+ * real prior context) followed by the trampoline entry address at
+ * new_sp+48, so the final `ret` below jumps there instead of into some
+ * prior caller.
+ */
+
+    .intel_syntax noprefix
+    .section .text
+
+.hidden sk_vm_switch_to
+
+    .global sk_vm_switch_to
+sk_vm_switch_to:
+    push rbp
+    push rbx
+    push r12
+    push r13
+    push r14
+    push r15
+
+    mov [rdi], rsp      /* *save_sp_out = rsp (this context's parked SP) */
+    mov rsp, rsi         /* rsp = new_sp (switch stacks) */
+
+    pop r15
+    pop r14
+    pop r13
+    pop r12
+    pop rbx
+    pop rbp
+    ret
+
+/*
+ * uint64_t sk_vm_switch_prime(uint64_t stack_top, void *entry);
+ *
+ * Builds the synthetic frame described above at the top of a fresh native
+ * stack, so the first ever sk_vm_switch_to() into it lands at `entry`
+ * instead of some real prior caller. Returns the resulting sp value to
+ * pass as sk_vm_switch_to()'s new_sp. Kept in this file (not C) so the
+ * layout can never drift from what sk_vm_switch_to() above actually
+ * expects -- one set of offsets, not two copies to keep in sync.
+ */
+.hidden sk_vm_switch_prime
+
+    .global sk_vm_switch_prime
+sk_vm_switch_prime:
+    mov rax, rdi
+    sub rax, 56
+    mov qword ptr [rax+0],  0    /* r15 */
+    mov qword ptr [rax+8],  0    /* r14 */
+    mov qword ptr [rax+16], 0    /* r13 */
+    mov qword ptr [rax+24], 0    /* r12 */
+    mov qword ptr [rax+32], 0    /* rbx */
+    mov qword ptr [rax+40], 0    /* rbp */
+    mov [rax+48], rsi             /* return address = entry */
+    ret