From d7745b49bebe3ce92c3841671e58c3fad24a0329 Mon Sep 17 00:00:00 2001 From: Robert Allan James Date: Sat, 26 Sep 2026 15:36:28 -0400 Subject: [PATCH] =?UTF-8?q?FABRIC-3.10.8=20=C2=A77.7:=20MC-3b=20plan=20--?= =?UTF-8?q?=20per-core=20IPI=20receivers,=20boot=20round-trip=20self-test?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Co-Authored-By: Claude Opus 5.5 --- FABRIC-3.10.8.md | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/FABRIC-3.10.8.md b/FABRIC-3.10.8.md index f6e5fe2d..55cd70cc 100644 --- a/FABRIC-3.10.8.md +++ b/FABRIC-3.10.8.md @@ -1081,3 +1081,26 @@ The boot hart HSM chose (0) is the one OpenSBI names as `Boot HART ID`. | riscv64 | `logs/20260926-151755` | same; 0 `timed out` | **MC-3a is complete.** Next: MC-3b, each worker core's interrupt controller and the IPI. + +### 7.7 MC-3b — waking a worker core (plan) + +**Change** (§7.2 item 3; nothing runs on the worker core yet): +- **Before marking itself online, each worker core sets up its own interrupt receiver** (`arch_smp_secondary_init()`), for the IPI only: + - amd64: its LAPIC enabled (SIVR, TPR 0), with a new IPI vector 0x22 and its own ISR stub. Vectors past 33 otherwise all land in the "255" default stub (the same trap the keyboard's vector 33 hit, `isr.S`). + - aarch64: its banked GIC CPU interface and SGI 0 enabled. Its target mask is read from its own banked `GICD_ITARGETSR0`. + - riscv64: `sie.SSIE`. +- **Sending** (`arch_smp_send_ipi()`): + - amd64: a fixed IPI through the ICR. + - aarch64: `GICD_SGIR` with the target mask. + - riscv64: SBI IPI `send_ipi` for its hartid. +- **Receiving.** Each ISA's interrupt handler recognises the IPI, counts it in the receiving core's block (`ipi_received`) and acknowledges it: LAPIC EOI; the GIC's full IAR value to EOIR, since an SGI's IAR carries its source CPU; `sip.SSIP` cleared on riscv64. Core 0's existing handlers are unchanged. +- **Parking with a way out.** The park step now lets exactly one interrupt in, without a lost-wake window: + - amd64: `sti; hlt; cli` (the `sti` shadow covers the `hlt`). + - aarch64 and riscv64: `wfi` with interrupts masked (it wakes on any pending, enabled interrupt), then unmask and mask again to take it. +- **Boot self-test** in `sk_smp_init()`: for each worker core, core 0 sends 3 IPIs one at a time, each waited for under a 100 ms bound, and prints the round trips. +- **The idle-point report** now logs a core's wakes together with its IPI count, when either changes. A wake without an IPI is the "spurious" figure. + +**Evidence (named in advance):** +- **All three ISAs:** `SMP: core 1: IPI round trips 3/3`, then one idle-point line with **3 wakes, 3 IPIs**, and no later line in the run (no further wake). +- **The standard sequence unchanged:** K-10 hashes, G byte-identical, all ok `3`, 0 B idle growth, 0 order violations, 0 double claims. +- **Host `ps -L` on aarch64 and riscv64:** `CPU 1/TCG` stays at about 0% after boot.