FABRIC-3.10.8 MC-1c: riscv64's second hart online and parked; MC-1 complete

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Harts from the DTB /cpus or, on QEMU (ACPI, no DTB), the MADT RINTC
entries; the boot hart is the one SBI HSM reports STARTED. SBI HSM
hart_start into ap_entry.S (stvec/satp copied, FPU on, tp set), park.
Hart 1 online in S-mode with its own block; its vCPU thread 0.0% on the
host. QEMU riscv64 -smp 2 -name debug-threads=on. All three ISAs now
boot two cores; 3-ISA acceptance clean.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>

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This commit is contained in:

Robert Allan James

2026-09-26 13:50:26 -04:00

co-authored by Claude Opus 5.5

parent 3a2ba5149f

commit c081bcf87a

11 changed files with 27828 additions and 8 deletions

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experiments/bare_metal/runs/doe-aarch64-20260926-133959.csv

experiments/bare_metal/runs/doe-amd64-20260926-133004.csv

experiments/bare_metal/runs/doe-riscv64-20260926-131910.csv