Reorganize source tree: kernel/, v3/, v4/ split and board infrastructure
Source tree reorganization: - Move StarForth v3 engine to v3/ (src/, include/, Makefile) - Move kernel to kernel/ (src/, include/, linker/, Makefile) - Create v4/ skeleton for F18-ISA golden model (DECOMPOSITION.md, JUSTIFICATION.md) - Move FABRIC-0..4.md to docs/fabric/ - Move ONTOLOGY.md and ROADMAP.md to docs/ Board infrastructure: - Add boards/ser5/, boards/raspi/, boards/milkv/, boards/zynq7020/ - Each board has board.mk (ISA, CPU flags, boot recipe) and README.md - Root Makefile becomes thin dispatcher: boot_image, all, clean, docs take TARGET - make boot_image TARGET=SER5|RASPI|MILKV builds one GPT/MBR image per board - ZYNQ7020 target exists but stops with clear error (ARMv7 port not built yet) - scripts/mkdiskimage.sh builds disk images for all boards Docs pipeline: - docs/book/ with LaTeX master (main.tex) and Makefile - pandoc converts Markdown to LaTeX at build time - Two Lua filters: table-widths.lua (wide tables wrap), code-breaks.lua (inline code breaks) - make docs builds single PDF (754 pages, 0 missing characters) - make docs TARGET=<board> adds board appendix - build/docs/<book|board>/meta.tex stamps git commit into PDF Bug fixes: - 42 include paths that only worked by accident now use correct relative paths - clang-18 hardcode replaced with configurable CC variable (fixed aarch64 build) - Pi 5: kernel_2712.img linked at 0x80000, .bss zeroed, memory reserved - Doxyfile, .clang-tidy, README.md, Kconfig paths updated Verified: - Hosted v3 build passes 1012 tests, 0 failures - SER5 image boots in QEMU (OVMF), POST passes, K exact (65536 = Q48_ONE) - Milk-V image boots in QEMU (OpenSBI + U-Boot + bootefi), POST passes - make clean TARGET=<board> removes only that board and its ISA objects - make all builds all boards, hosted v3, and docs in one run Co-authored-by: Junie <junie@jetbrains.com>
This commit is contained in:
rajames
@@ -0,0 +1,556 @@
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/*
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StarForth — Steady-State Virtual Machine Runtime
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Copyright (c) 2023–2025 Robert A. James
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All rights reserved.
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This file is part of the StarForth project.
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Licensed under the StarForth License, Version 1.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at:
|
||||
https://github.com/star.4th@proton.me/StarForth/LICENSE.txt
|
||||
|
||||
This software is provided "AS IS", WITHOUT WARRANTY OF ANY KIND,
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||||
express or implied, including but not limited to the warranties of
|
||||
merchantability, fitness for a particular purpose, and noninfringement.
|
||||
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
|
||||
StarForth — Steady-State Virtual Machine Runtime
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Copyright (c) 2023–2025 Robert A. James
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All rights reserved.
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This file is part of the StarForth project.
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Licensed under the StarForth License, Version 1.0 (the "License");
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||||
you may not use this file except in compliance with the License.
|
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||||
You may obtain a copy of the License at:
|
||||
https://github.com/star.4th@proton.me/StarForth/LICENSE.txt
|
||||
|
||||
This software is provided "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
express or implied, including but not limited to the warranties of
|
||||
merchantability, fitness for a particular purpose, and noninfringement.
|
||||
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
|
||||
*/
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#ifndef VM_INNER_INTERP_ARM64_H
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#define VM_INNER_INTERP_ARM64_H
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#include "vm.h"
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/*
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* ARM64 DIRECT-THREADED INNER INTERPRETER
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* ========================================
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*
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* ARM64 advantages over x86_64:
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* - More registers (31 vs 16)
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* - Better branch prediction
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* - Conditional execution
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* - Load/store with auto-increment
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* - Lower power consumption
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*
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* Register Allocation (using callee-saved registers):
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* - x19: VM pointer (callee-saved)
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* - x20: Instruction Pointer (IP)
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* - x21: Data Stack Pointer (DSP) - actual pointer
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* - x22: Return Stack Pointer (RSP) - actual pointer
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* - x23: Top of Stack cache (TOS) - keep in register
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* - x24-x28: Available for future use
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*
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* Why more registers help:
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* - Can keep TOS in register (x23)
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* - More scratch registers for complex operations
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* - Less memory traffic
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*
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* Performance on Raspberry Pi 4:
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* - Expected 3-5x speedup for threaded code
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* - Better than x86_64 due to more registers
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* - Lower power = less thermal throttling
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*/
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#ifndef USE_DIRECT_THREADING
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#define USE_DIRECT_THREADING 0
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#endif
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#if USE_DIRECT_THREADING
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/*
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* NEXT macro - ARM64 version
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*
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* On ARM64, we can use:
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* - Load with post-increment (ldr x0, [x20], #8)
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* - Indirect branch (br x0)
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*/
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#define NEXT_ARM64() \
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__asm__ __volatile__ ( \
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"ldr x0, [x20], #8\n\t" /* Load word ptr from [IP], IP += 8 */ \
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"br x0\n\t" /* Branch to word */ \
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::: "x0", "memory" \
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)
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/*
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* DOCOL - Enter a colon definition (ARM64)
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*/
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static inline void vm_docol_arm64(VM *vm) {
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__asm__ __volatile__(
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/* Save current IP on return stack */
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"str x20, [x22], #8\n\t" /* [RSP] = IP, RSP += 8 */
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/* IP = address of colon definition body */
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"ldr x0, %[entry]\n\t"
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"ldr x20, [x0]\n\t" /* IP = entry->code_field */
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/* Continue with NEXT */
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"ldr x0, [x20], #8\n\t"
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"br x0\n\t"
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:
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: [entry]"m"(vm->current_executing_entry)
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: "x0", "x20", "x22", "memory"
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);
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}
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/*
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* EXIT - Return from a colon definition (ARM64)
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*/
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static inline void vm_exit_arm64(void) {
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__asm__ __volatile__(
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/* Restore IP from return stack */
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"ldr x20, [x22, #-8]!\n\t" /* RSP -= 8, IP = [RSP] (pre-decrement) */
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/* Continue with NEXT */
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"ldr x0, [x20], #8\n\t"
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"br x0\n\t"
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::: "x0", "x20", "x22", "memory"
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);
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}
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/*
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* Setup registers before entering inner loop
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*/
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static inline void vm_setup_registers_arm64(VM *vm) {
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__asm__ __volatile__(
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/* Save callee-saved registers (required by ARM64 ABI) */
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"stp x19, x20, [sp, #-80]!\n\t"
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"stp x21, x22, [sp, #16]\n\t"
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"stp x23, x24, [sp, #32]\n\t"
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"stp x25, x26, [sp, #48]\n\t"
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"stp x27, x28, [sp, #64]\n\t"
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/* Load VM pointer */
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"mov x19, %[vm]\n\t" /* x19 = VM pointer */
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/* Load IP */
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"ldr x20, %[ip]\n\t" /* x20 = IP */
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/* Calculate data stack pointer */
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"ldr w0, %[dsp]\n\t"
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"ldr x1, %[dstack]\n\t"
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"add x21, x1, x0, sxtw #3\n\t" /* x21 = &data_stack[dsp] */
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/* Calculate return stack pointer */
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"ldr w0, %[rsp]\n\t"
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"ldr x1, %[rstack]\n\t"
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"add x22, x1, x0, sxtw #3\n\t" /* x22 = &return_stack[rsp] */
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/* Load TOS into x23 if stack not empty */
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"ldr w0, %[dsp]\n\t"
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"cmp w0, #0\n\t"
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"b.lt 1f\n\t"
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"ldr x23, [x21]\n\t" /* x23 = TOS (cached) */
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"1:\n\t"
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:
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: [vm]"r"(vm),
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[ip]"m"(vm->ip),
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[dsp]"m"(vm->dsp),
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[rsp]"m"(vm->rsp),
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[dstack]"m"(vm->data_stack),
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[rstack]"m"(vm->return_stack)
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: "x0", "x1", "x19", "x20", "x21", "x22", "x23", "x24",
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"x25", "x26", "x27", "x28", "memory"
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);
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}
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/*
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* Save registers back to VM structure
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*/
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static inline void vm_save_registers_arm64(VM *vm) {
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__asm__ __volatile__(
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/* Save TOS back to stack */
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"str x23, [x21]\n\t"
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/* Save IP */
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"str x20, %[ip]\n\t"
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/* Calculate and save dsp */
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"ldr x0, %[dstack]\n\t"
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"sub x1, x21, x0\n\t"
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"lsr x1, x1, #3\n\t" /* / 8 */
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"str w1, %[dsp]\n\t"
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/* Calculate and save rsp */
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"ldr x0, %[rstack]\n\t"
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"sub x1, x22, x0\n\t"
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"lsr x1, x1, #3\n\t"
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"str w1, %[rsp]\n\t"
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/* Restore callee-saved registers */
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"ldp x27, x28, [sp, #64]\n\t"
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"ldp x25, x26, [sp, #48]\n\t"
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"ldp x23, x24, [sp, #32]\n\t"
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"ldp x21, x22, [sp, #16]\n\t"
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"ldp x19, x20, [sp], #80\n\t"
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: [ip]"=m"(vm->ip),
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[dsp]"=m"(vm->dsp),
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[rsp]"=m"(vm->rsp)
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: [dstack]"m"(vm->data_stack),
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[rstack]"m"(vm->return_stack)
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: "x0", "x1", "memory"
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);
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}
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/**
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* @defgroup primitives Fast Primitive Word Implementations
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* @brief Register-based stack primitives optimized for ARM64
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*
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* Key optimization: TOS stays in x23, avoiding memory traffic
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* @{
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*/
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/** @brief DUP primitive - duplicates top of stack item */
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#define PRIM_DUP_ARM64() \
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__asm__ __volatile__ ( \
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"str x23, [x21, #8]!\n\t" /* Store TOS, advance DSP */ \
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::: "x21", "memory" \
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)
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/* DROP - remove top of stack */
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#define PRIM_DROP_ARM64() \
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__asm__ __volatile__ ( \
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"ldr x23, [x21], #-8\n\t" /* Load new TOS, decrement DSP */ \
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::: "x21", "x23", "memory" \
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)
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/* SWAP - swap top two stack items */
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#define PRIM_SWAP_ARM64() \
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__asm__ __volatile__ ( \
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"ldr x0, [x21]\n\t" /* Load NOS */ \
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"str x23, [x21]\n\t" /* Store TOS to NOS position */ \
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"mov x23, x0\n\t" /* TOS = old NOS */ \
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::: "x0", "x23", "memory" \
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)
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/* OVER - copy second item to top */
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#define PRIM_OVER_ARM64() \
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__asm__ __volatile__ ( \
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"ldr x0, [x21]\n\t" /* Load NOS */ \
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"str x23, [x21, #8]!\n\t" /* Store TOS, advance DSP */ \
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"mov x23, x0\n\t" /* TOS = NOS */ \
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::: "x0", "x21", "x23", "memory" \
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)
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/* ROT - rotate top three items */
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#define PRIM_ROT_ARM64() \
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__asm__ __volatile__ ( \
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"ldr x0, [x21]\n\t" /* Load item2 */ \
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"ldr x1, [x21, #-8]\n\t" /* Load item3 */ \
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"str x1, [x21]\n\t" /* item3 -> NOS */ \
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"str x23, [x21, #-8]\n\t" /* TOS -> item3 */ \
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"mov x23, x0\n\t" /* item2 -> TOS */ \
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::: "x0", "x1", "x23", "memory" \
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)
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||||
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/* + - add top two stack items */
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#define PRIM_PLUS_ARM64() \
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__asm__ __volatile__ ( \
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"ldr x0, [x21], #-8\n\t" /* Load NOS, decrement DSP */ \
|
||||
"add x23, x23, x0\n\t" /* TOS = TOS + NOS */ \
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||||
::: "x0", "x21", "x23" \
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)
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||||
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||||
/* - - subtract top from second */
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#define PRIM_MINUS_ARM64() \
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__asm__ __volatile__ ( \
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"ldr x0, [x21], #-8\n\t" /* Load NOS, decrement DSP */ \
|
||||
"sub x23, x0, x23\n\t" /* TOS = NOS - TOS */ \
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||||
::: "x0", "x21", "x23" \
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)
|
||||
|
||||
/* * - multiply top two stack items */
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#define PRIM_STAR_ARM64() \
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__asm__ __volatile__ ( \
|
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"ldr x0, [x21], #-8\n\t" /* Load NOS, decrement DSP */ \
|
||||
"mul x23, x23, x0\n\t" /* TOS = TOS * NOS */ \
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::: "x0", "x21", "x23" \
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)
|
||||
|
||||
/* / - divide second by top */
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||||
#define PRIM_SLASH_ARM64() \
|
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__asm__ __volatile__ ( \
|
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"ldr x0, [x21], #-8\n\t" /* Load NOS (dividend), decrement DSP */ \
|
||||
"sdiv x23, x0, x23\n\t" /* TOS = NOS / TOS */ \
|
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::: "x0", "x21", "x23" \
|
||||
)
|
||||
|
||||
/* MOD - modulo */
|
||||
#define PRIM_MOD_ARM64() \
|
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__asm__ __volatile__ ( \
|
||||
"ldr x0, [x21], #-8\n\t" /* Load NOS, decrement DSP */ \
|
||||
"sdiv x1, x0, x23\n\t" /* quotient = NOS / TOS */ \
|
||||
"msub x23, x1, x23, x0\n\t" /* TOS = NOS - quotient * TOS */ \
|
||||
::: "x0", "x1", "x21", "x23" \
|
||||
)
|
||||
|
||||
/* AND - bitwise and */
|
||||
#define PRIM_AND_ARM64() \
|
||||
__asm__ __volatile__ ( \
|
||||
"ldr x0, [x21], #-8\n\t" \
|
||||
"and x23, x23, x0\n\t" \
|
||||
::: "x0", "x21", "x23" \
|
||||
)
|
||||
|
||||
/* OR - bitwise or */
|
||||
#define PRIM_OR_ARM64() \
|
||||
__asm__ __volatile__ ( \
|
||||
"ldr x0, [x21], #-8\n\t" \
|
||||
"orr x23, x23, x0\n\t" \
|
||||
::: "x0", "x21", "x23" \
|
||||
)
|
||||
|
||||
/* XOR - bitwise xor */
|
||||
#define PRIM_XOR_ARM64() \
|
||||
__asm__ __volatile__ ( \
|
||||
"ldr x0, [x21], #-8\n\t" \
|
||||
"eor x23, x23, x0\n\t" \
|
||||
::: "x0", "x21", "x23" \
|
||||
)
|
||||
|
||||
/* INVERT - bitwise not */
|
||||
#define PRIM_INVERT_ARM64() \
|
||||
__asm__ __volatile__ ( \
|
||||
"mvn x23, x23\n\t" \
|
||||
::: "x23" \
|
||||
)
|
||||
|
||||
/* NEGATE - two's complement */
|
||||
#define PRIM_NEGATE_ARM64() \
|
||||
__asm__ __volatile__ ( \
|
||||
"neg x23, x23\n\t" \
|
||||
::: "x23" \
|
||||
)
|
||||
|
||||
/* @ - fetch cell from memory */
|
||||
#define PRIM_FETCH_ARM64() \
|
||||
__asm__ __volatile__ ( \
|
||||
"ldr x0, [x19]\n\t" /* Load VM->memory */ \
|
||||
"ldr x23, [x0, x23]\n\t" /* TOS = memory[TOS] */ \
|
||||
::: "x0", "x23", "memory" \
|
||||
)
|
||||
|
||||
/* ! - store cell to memory */
|
||||
#define PRIM_STORE_ARM64() \
|
||||
__asm__ __volatile__ ( \
|
||||
"ldr x0, [x21], #-8\n\t" /* Load address, decrement DSP */ \
|
||||
"ldr x1, [x19]\n\t" /* Load VM->memory */ \
|
||||
"str x23, [x1, x0]\n\t" /* memory[addr] = value */ \
|
||||
"ldr x23, [x21]\n\t" /* Load new TOS */ \
|
||||
::: "x0", "x1", "x21", "x23", "memory" \
|
||||
)
|
||||
|
||||
/* C@ - fetch byte from memory */
|
||||
#define PRIM_C_FETCH_ARM64() \
|
||||
__asm__ __volatile__ ( \
|
||||
"ldr x0, [x19]\n\t" \
|
||||
"ldrb w23, [x0, x23]\n\t" /* Load byte, zero-extend */ \
|
||||
::: "x0", "x23", "memory" \
|
||||
)
|
||||
|
||||
/* C! - store byte to memory */
|
||||
#define PRIM_C_STORE_ARM64() \
|
||||
__asm__ __volatile__ ( \
|
||||
"ldr x0, [x21], #-8\n\t" \
|
||||
"ldr x1, [x19]\n\t" \
|
||||
"strb w23, [x1, x0]\n\t" /* Store byte */ \
|
||||
"ldr x23, [x21]\n\t" \
|
||||
::: "x0", "x1", "x21", "x23", "memory" \
|
||||
)
|
||||
|
||||
/* >R - push to return stack */
|
||||
#define PRIM_TO_R_ARM64() \
|
||||
__asm__ __volatile__ ( \
|
||||
"str x23, [x22], #8\n\t" /* Store to RS, advance RSP */ \
|
||||
"ldr x23, [x21], #-8\n\t" /* Load new TOS, decrement DSP */ \
|
||||
::: "x21", "x22", "x23", "memory" \
|
||||
)
|
||||
|
||||
/* R> - pop from return stack */
|
||||
#define PRIM_R_FROM_ARM64() \
|
||||
__asm__ __volatile__ ( \
|
||||
"str x23, [x21, #8]!\n\t" /* Store TOS, advance DSP */ \
|
||||
"ldr x23, [x22, #-8]!\n\t" /* Load from RS, decrement RSP */ \
|
||||
::: "x21", "x22", "x23", "memory" \
|
||||
)
|
||||
|
||||
/* R@ - copy top of return stack to data stack */
|
||||
#define PRIM_R_FETCH_ARM64() \
|
||||
__asm__ __volatile__ ( \
|
||||
"str x23, [x21, #8]!\n\t" /* Store TOS, advance DSP */ \
|
||||
"ldr x23, [x22, #-8]\n\t" /* Load from RS (don't pop) */ \
|
||||
::: "x21", "x23", "memory" \
|
||||
)
|
||||
|
||||
/* 2DUP - duplicate top two items */
|
||||
#define PRIM_2DUP_ARM64() \
|
||||
__asm__ __volatile__ ( \
|
||||
"ldr x0, [x21]\n\t" /* Load NOS */ \
|
||||
"stp x0, x23, [x21, #8]\n\t" /* Store pair */ \
|
||||
"add x21, x21, #16\n\t" /* DSP += 2 */ \
|
||||
::: "x0", "x21", "memory" \
|
||||
)
|
||||
|
||||
/* 2DROP - drop top two items */
|
||||
#define PRIM_2DROP_ARM64() \
|
||||
__asm__ __volatile__ ( \
|
||||
"ldr x23, [x21, #-8]\n\t" /* Load new TOS */ \
|
||||
"sub x21, x21, #16\n\t" /* DSP -= 2 */ \
|
||||
::: "x21", "x23", "memory" \
|
||||
)
|
||||
|
||||
/* 0= - test if zero */
|
||||
#define PRIM_ZERO_EQUALS_ARM64() \
|
||||
__asm__ __volatile__ ( \
|
||||
"cmp x23, #0\n\t" \
|
||||
"cset x23, eq\n\t" /* Set to 1 if zero, else 0 */ \
|
||||
"neg x23, x23\n\t" /* Convert to -1 (true flag) */ \
|
||||
::: "x23", "cc" \
|
||||
)
|
||||
|
||||
/* 0< - test if negative */
|
||||
#define PRIM_ZERO_LESS_ARM64() \
|
||||
__asm__ __volatile__ ( \
|
||||
"cmp x23, #0\n\t" \
|
||||
"cset x23, lt\n\t" \
|
||||
"neg x23, x23\n\t" \
|
||||
::: "x23", "cc" \
|
||||
)
|
||||
|
||||
/* = - test equality */
|
||||
#define PRIM_EQUALS_ARM64() \
|
||||
__asm__ __volatile__ ( \
|
||||
"ldr x0, [x21], #-8\n\t" \
|
||||
"cmp x0, x23\n\t" \
|
||||
"cset x23, eq\n\t" \
|
||||
"neg x23, x23\n\t" \
|
||||
::: "x0", "x21", "x23", "cc" \
|
||||
)
|
||||
|
||||
/* < - test less than (signed) */
|
||||
#define PRIM_LESS_ARM64() \
|
||||
__asm__ __volatile__ ( \
|
||||
"ldr x0, [x21], #-8\n\t" \
|
||||
"cmp x0, x23\n\t" \
|
||||
"cset x23, lt\n\t" \
|
||||
"neg x23, x23\n\t" \
|
||||
::: "x0", "x21", "x23", "cc" \
|
||||
)
|
||||
|
||||
/* > - test greater than (signed) */
|
||||
#define PRIM_GREATER_ARM64() \
|
||||
__asm__ __volatile__ ( \
|
||||
"ldr x0, [x21], #-8\n\t" \
|
||||
"cmp x0, x23\n\t" \
|
||||
"cset x23, gt\n\t" \
|
||||
"neg x23, x23\n\t" \
|
||||
::: "x0", "x21", "x23", "cc" \
|
||||
)
|
||||
|
||||
/*
|
||||
* Control flow primitives
|
||||
*/
|
||||
|
||||
/* BRANCH - unconditional branch */
|
||||
#define PRIM_BRANCH_ARM64() \
|
||||
__asm__ __volatile__ ( \
|
||||
"ldr x0, [x20]\n\t" /* Load offset */ \
|
||||
"add x20, x20, x0\n\t" /* IP += offset */ \
|
||||
::: "x0", "x20", "memory" \
|
||||
)
|
||||
|
||||
/* 0BRANCH - branch if TOS is zero */
|
||||
#define PRIM_ZBRANCH_ARM64() \
|
||||
__asm__ __volatile__ ( \
|
||||
"ldr x0, [x20]\n\t" /* Load offset */ \
|
||||
"cmp x23, #0\n\t" \
|
||||
"add x1, x20, x0\n\t" /* Calculate target */ \
|
||||
"add x2, x20, #8\n\t" /* Calculate skip */ \
|
||||
"csel x20, x1, x2, eq\n\t" /* Select target if zero */ \
|
||||
"ldr x23, [x21], #-8\n\t" /* Load new TOS */ \
|
||||
::: "x0", "x1", "x2", "x20", "x21", "x23", "cc", "memory" \
|
||||
)
|
||||
|
||||
/* EXECUTE - execute word whose xt is on stack */
|
||||
#define PRIM_EXECUTE_ARM64() \
|
||||
__asm__ __volatile__ ( \
|
||||
"ldr x23, [x21], #-8\n\t" /* Load new TOS */ \
|
||||
"br x0\n\t" /* Branch to xt */ \
|
||||
::: "x0", "x21", "x23", "memory" \
|
||||
)
|
||||
|
||||
#else /* !USE_DIRECT_THREADING */
|
||||
|
||||
/* Fallback definitions */
|
||||
#define NEXT_ARM64() do {} while(0)
|
||||
#define vm_setup_registers_arm64(vm) do {} while(0)
|
||||
#define vm_save_registers_arm64(vm) do {} while(0)
|
||||
|
||||
#endif /* USE_DIRECT_THREADING */
|
||||
|
||||
/*
|
||||
* ============================================================================
|
||||
* RASPBERRY PI 4 PERFORMANCE TUNING
|
||||
* ============================================================================
|
||||
*
|
||||
* Cache Optimization:
|
||||
* -------------------
|
||||
* 1. Align VM structure to cache line (64 bytes):
|
||||
* typedef struct VM { ... } __attribute__((aligned(64))) VM;
|
||||
*
|
||||
* 2. Separate hot/cold data:
|
||||
* - Keep stacks, IP, SP together (hot)
|
||||
* - Move error handling, I/O to separate structure (cold)
|
||||
*
|
||||
* 3. Prefetch dictionary entries:
|
||||
* vm_prefetch(vm->latest);
|
||||
* vm_prefetch(vm->latest->link);
|
||||
*
|
||||
* Thermal Management:
|
||||
* -------------------
|
||||
* 1. Monitor temperature:
|
||||
* vcgencmd measure_temp
|
||||
*
|
||||
* 2. Add heatsink or fan for sustained load
|
||||
*
|
||||
* 3. Reduce CPU frequency if needed:
|
||||
* echo 1200000 > /sys/devices/system/cpu/cpu0/cpufreq/scaling_max_freq
|
||||
*
|
||||
* Power Optimization:
|
||||
* -------------------
|
||||
* 1. Use WFE (Wait For Event) in idle loops
|
||||
* 2. Disable unused cores if single-threaded
|
||||
* 3. Use NEON for parallel operations (lower power than scalar)
|
||||
*
|
||||
* Build Configuration:
|
||||
* --------------------
|
||||
* Native: -march=armv8-a+crc+simd -mtune=cortex-a72
|
||||
* Cross: CC=aarch64-linux-gnu-gcc
|
||||
*
|
||||
* ============================================================================
|
||||
*/
|
||||
|
||||
#endif /* VM_INNER_INTERP_ARM64_H */
|
||||
Reference in New Issue
Block a user