starkernel: converge the tick path and wire the adaptive heartbeat (item 0.8)
Introduces src/starkernel/heartbeat.c as the shared top/bottom-half implementation of heartbeat_init/tick/service/ticks/trust/state, replacing the per-architecture duplicates in amd64/riscv64/aarch64 timer.c. Each arch's timer.c now contributes only heartbeat_read_counter() (rdtsc / rdtime / CNTPCT_EL0). Per the GAP-A1 ruling the top half stays counter+ latch only; heartbeat_service() (called every REPL idle iteration, unconditionally per FABRIC.md's fidelity note) does the window/variance/ trust work outside interrupt context. vm_tick()'s call sites are unchanged -- the engine still runs on the virtual tick. Per FABRIC.md §26 (ruled 2026-08-03): wires Loop #7's execution-derived stable/volatile signal into the physical re-arm period. vm_runtime.c's existing Loop #7 site now calls heartbeat_set_adaptive_period_ns() with tick_target_ns ratio-rescaled onto a 10ms kernel base (not the hosted 10us HEARTBEAT_TICK_NS -- see §26.3 for the scale mismatch). Each architecture's re-arm function (apic_timer_rearm() on amd64/aarch64, riscv64_timer_rearm()) now converts heartbeat_next_period_ns() to its own raw counter units instead of a fixed constant; amd64 gained a rearm function it didn't previously need, since periodic-mode auto-reload never required one before this item. Verified: all three architectures build with no new warnings and boot cleanly to ok> with dict_hash=0x3d4e1daf289da94f, unchanged from the pre-change baseline -- no regression. Verified NOT achieved: live re-arm period variation under load. A temporary diagnostic (added and reverted) confirmed Loop #7 never actually fired during a live QEMU session -- a synthetic word-execution loop drove ~6,500 executions, past the 1000-tick inference frequency, without tripping vm_tick_inference_engine()'s pre-existing !vm->rolling_window.is_warm gate. That gate predates this item and was not investigated -- out of scope. FABRIC.md's Done-when is amended to record this honestly rather than claim it. Punch list §25 item 0.8 complete (per amended, weaker acceptance -- see the item's own annotation). Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
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co-authored by
Claude Sonnet 5
parent
da4cb14702
commit
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@@ -32,6 +32,7 @@
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#include "apic.h"
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#include "uefi.h"
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#include "console.h"
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#include "timer.h"
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#include <stdint.h>
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/* Defined in arch.c (item 0.4). Same extern-in-place convention as
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@@ -92,6 +93,7 @@ static inline uint32_t mmio_read32(uintptr_t base, uint32_t offset)
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static uint32_t s_timer_ppi = TIMER_PPI_EL1;
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static uint64_t s_timer_period_tsc = 0;
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static uint64_t s_counter_hz_apic = 0; /* CNTFRQ_EL0 (item 0.8/§26) */
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/**
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* @brief Initialise the GICv2 distributor and CPU interface (M4 milestone).
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@@ -227,6 +229,7 @@ int apic_timer_init(uint64_t tsc_hz, uint32_t tick_hz)
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} else {
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s_timer_period_tsc = 10000000;
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}
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s_counter_hz_apic = tsc_hz;
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return 0;
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}
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@@ -305,11 +308,23 @@ void apic_timer_start(void)
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* @c heartbeat_tick() — same ordering discipline as
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* @c riscv64_timer_rearm() (item 0.3): re-arm first, so a fault in the
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* rest of the handler cannot also cost the next tick.
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*
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* The step written is @c heartbeat_next_period_ns() (item 0.8, §26)
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* converted to @c CNTPCT_EL0 ticks via @c s_counter_hz_apic, not the fixed
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* @c s_timer_period_tsc @c apic_timer_start() used for the very first arm
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* -- that value remains @c apic_timer_period_tsc()'s return for
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* @c heartbeat_init()'s initial @c expected_delta, unchanged.
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*/
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void apic_timer_rearm(void)
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{
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uint64_t period_ticks = (s_counter_hz_apic > 0)
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? (heartbeat_next_period_ns() * s_counter_hz_apic) / 1000000000ULL
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: s_timer_period_tsc;
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if (period_ticks == 0) {
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period_ticks = 1;
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}
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/* uint64_t, zero-extended -- see apic_timer_start() for why. */
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uint64_t tval = (uint64_t)(uint32_t)s_timer_period_tsc;
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uint64_t tval = (uint64_t)(uint32_t)period_ticks;
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if (aarch64_current_el() == 2) {
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__asm__ volatile ("msr cnthp_tval_el2, %0" :: "r"(tval));
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