FABRIC-3.10.8 MC-1a: the core table, and amd64's second core online and parked
hal/smp.c: dense logical core ids, a heap-sized core table, one-at-a-time bring-up under a 1 s bound, park-wake reporting at the idle point. amd64: MADT enumeration, a relocation-free real->long-mode trampoline copied below 1 MiB, INIT-SIPI-SIPI via the LAPIC ICR; QEMU -smp 2. Core 1 reports online with GS on its own block, parks with 0 wakes; aarch64/riscv64 report 1 core until MC-1b/c. 3-ISA acceptance clean. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
This commit is contained in:
Robert Allan James
co-authored by
Claude Opus 5.5
Claude Opus 5.5
parent
8c068e00e3
commit
24bde47481
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/*
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StarForth — Steady-State Virtual Machine Runtime
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Copyright (c) 2023–2025 Robert A. James
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All rights reserved.
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This file is part of the StarForth project.
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Licensed under the StarForth License, Version 1.0 (the "License");
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you may not use this file except in compliance with the License.
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*/
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/**
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* smp.c (amd64) - secondary-core bring-up, FABRIC-3.10.8 MC-1a.
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*
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* Cores come from the MADT's enabled Local APIC entries. Each is started
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* with INIT, 10 ms, STARTUP, 200 us, STARTUP into ap_trampoline.S, copied
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* into a conventional-memory page below 1 MiB taken from the UEFI memory
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* map. The trampoline enters long mode on the boot core's own control
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* state and calls sk_smp_secondary_main() with its GS base already set.
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*
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* Limit (recorded for SER5): the trampoline loads CR3 in 32-bit mode, so
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* the page tables must lie below 4 GiB; a start is refused otherwise.
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*/
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#include "starkernel/smp.h"
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#include "starkernel/apic.h"
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#include "starkernel/timer.h"
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#include "starkernel/console.h"
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#include "uefi.h"
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extern char sk_ap_tramp_start[], sk_ap_tramp_end[];
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extern char sk_ap_tr_pm_jmp[], sk_ap_tr_lm_jmp[], sk_ap_tr_pm32[], sk_ap_tr_lm64[];
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extern char sk_ap_tr_gdt[], sk_ap_tr_gdtr[], sk_ap_tr_data[];
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/* The trampoline's data block (ap_trampoline.S, D_* offsets). */
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typedef struct __attribute__((packed)) {
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uint64_t cr0, cr3, cr4_boot, cr4, efer, pat, xcr0, xcr0_valid;
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uint64_t percpu, stack, entry;
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uint16_t kgdt_limit; uint64_t kgdt_base;
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uint16_t kidt_limit; uint64_t kidt_base;
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} ap_tramp_data_t;
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#define CR4_PCIDE (1ull << 17)
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#define CR4_OSXSAVE (1ull << 18)
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#define ICR_INIT 0x00004500u /* INIT, level assert */
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#define ICR_STARTUP 0x00004600u /* STARTUP; low byte = vector (page number) */
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/* ---- MADT ---------------------------------------------------------------- */
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typedef struct __attribute__((packed)) {
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uint8_t signature[8];
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uint8_t checksum;
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uint8_t oem_id[6];
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uint8_t revision;
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uint32_t rsdt_address;
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uint32_t length;
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uint64_t xsdt_address;
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} smp_rsdp_t;
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typedef struct __attribute__((packed)) {
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uint8_t signature[4];
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uint32_t length;
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uint8_t rest[28];
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} smp_sdt_t;
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static int sig_eq(const uint8_t *p, const char *s, int n)
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{
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int i;
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for (i = 0; i < n; i++) if (p[i] != (uint8_t)s[i]) return 0;
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return 1;
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}
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static const uint8_t *find_madt(void *rsdp_ptr)
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{
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const smp_rsdp_t *r = (const smp_rsdp_t *)rsdp_ptr;
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const smp_sdt_t *xsdt;
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const uint64_t *ent;
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uint32_t n, i;
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if (!r || !sig_eq(r->signature, "RSD PTR ", 8) || r->revision < 2 || !r->xsdt_address) return 0;
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xsdt = (const smp_sdt_t *)(uintptr_t)r->xsdt_address;
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if (!sig_eq(xsdt->signature, "XSDT", 4) || xsdt->length <= 36u) return 0;
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n = (xsdt->length - 36u) / 8u;
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ent = (const uint64_t *)((const uint8_t *)xsdt + 36u);
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for (i = 0; i < n; i++) {
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const smp_sdt_t *sdt = (const smp_sdt_t *)(uintptr_t)ent[i];
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if (sdt && sig_eq(sdt->signature, "APIC", 4)) return (const uint8_t *)sdt;
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}
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return 0;
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}
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static int id_seen(const uint64_t *ids, uint32_t n, uint64_t id)
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{
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uint32_t i;
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for (i = 0; i < n; i++) if (ids[i] == id) return 1;
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return 0;
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}
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/* Enabled type-0 (Local APIC) entries, then type-9 (x2APIC) entries whose
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* id fits xAPIC (<= 255) and was not already listed. */
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uint32_t arch_smp_enumerate(BootInfo *boot_info, uint64_t *hw_ids, uint32_t cap)
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{
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const uint8_t *madt = find_madt(boot_info ? boot_info->acpi_table : (void *)0);
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const uint8_t *p, *end;
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uint32_t n = 0, pass;
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if (!madt) {
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if (cap) hw_ids[0] = apic_id();
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return 1;
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}
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end = madt + ((const smp_sdt_t *)madt)->length;
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for (pass = 0; pass < 2; pass++) {
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for (p = madt + 44; p + 2 <= end; p += p[1]) {
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uint64_t id;
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uint32_t flags;
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if (p[1] == 0 || p + p[1] > end) break;
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if (pass == 0 && p[0] == 0 && p[1] >= 8) {
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id = p[3];
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flags = (uint32_t)p[4] | ((uint32_t)p[5] << 8) | ((uint32_t)p[6] << 16) | ((uint32_t)p[7] << 24);
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} else if (pass == 1 && p[0] == 9 && p[1] >= 16) {
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id = (uint64_t)p[4] | ((uint64_t)p[5] << 8) | ((uint64_t)p[6] << 16) | ((uint64_t)p[7] << 24);
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flags = (uint32_t)p[8] | ((uint32_t)p[9] << 8) | ((uint32_t)p[10] << 16) | ((uint32_t)p[11] << 24);
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if (id > 255u) continue;
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} else {
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continue;
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}
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if (!(flags & 1u)) continue; /* not enabled */
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if (cap) {
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if (id_seen(hw_ids, n < cap ? n : cap, id)) continue;
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if (n < cap) hw_ids[n] = id;
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}
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n++;
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}
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}
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if (n == 0) {
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if (cap) hw_ids[0] = apic_id();
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return 1;
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}
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return n;
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}
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uint64_t arch_smp_boot_hw_id(void) { return apic_id(); }
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void arch_smp_park_once(void)
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{
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__asm__ volatile ("cli; hlt" ::: "memory");
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}
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/* ---- the trampoline page ------------------------------------------------- */
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static uint64_t g_tramp_page; /* 0 = not chosen yet */
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/* The lowest conventional page in [0x1000, 1 MiB) whose whole 4 KiB is
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* free in the UEFI memory map. */
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static uint64_t pick_tramp_page(BootInfo *bi)
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{
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uint64_t best = 0;
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UINTN n, i;
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if (!bi || !bi->memory_map || !bi->memory_map_descriptor_size) return 0;
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n = bi->memory_map_size / bi->memory_map_descriptor_size;
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for (i = 0; i < n; i++) {
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const EFI_MEMORY_DESCRIPTOR *d = (const EFI_MEMORY_DESCRIPTOR *)
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((const uint8_t *)bi->memory_map + i * bi->memory_map_descriptor_size);
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uint64_t start, end;
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if (d->Type != EfiConventionalMemory) continue;
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start = d->PhysicalStart;
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end = start + d->NumberOfPages * 4096ull;
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if (start < 0x1000ull) start = 0x1000ull;
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start = (start + 0xFFFull) & ~0xFFFull;
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if (start + 4096ull > end || start + 4096ull > 0x100000ull) continue;
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if (!best || start < best) best = start;
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}
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return best;
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}
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static uint64_t rdmsr64(uint32_t msr)
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{
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uint32_t lo, hi;
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__asm__ volatile ("rdmsr" : "=a"(lo), "=d"(hi) : "c"(msr));
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return ((uint64_t)hi << 32) | lo;
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}
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static void wait_us(uint64_t us)
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{
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uint64_t hz = timer_tsc_hz(), t0 = heartbeat_read_counter();
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uint64_t budget = hz ? (hz / 1000000u) * us : 0;
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uint64_t spin = us * 1000u; /* only if the counter's rate is unknown */
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while (hz ? (heartbeat_read_counter() - t0 < budget) : (spin-- > 0)) {
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__asm__ volatile ("pause");
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}
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}
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int arch_smp_start(BootInfo *boot_info, sk_percpu_t *pc, void *stack_top)
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{
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uint8_t *page;
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size_t len = (size_t)(sk_ap_tramp_end - sk_ap_tramp_start), k;
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ap_tramp_data_t *d;
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uint64_t cr0, cr3, cr4;
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struct __attribute__((packed)) { uint16_t limit; uint64_t base; } gdtr, idtr;
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uint32_t T;
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if (pc->hw_id > 255u || len > 4096u) return -1;
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if (!g_tramp_page) g_tramp_page = pick_tramp_page(boot_info);
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if (!g_tramp_page) {
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console_println("SMP: no conventional page below 1 MiB for the trampoline");
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return -1;
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}
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__asm__ volatile ("mov %%cr0, %0" : "=r"(cr0));
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__asm__ volatile ("mov %%cr3, %0" : "=r"(cr3));
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__asm__ volatile ("mov %%cr4, %0" : "=r"(cr4));
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if (cr3 >> 32) {
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console_println("SMP: page tables above 4 GiB -- the trampoline cannot load CR3");
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return -1;
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}
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__asm__ volatile ("sgdt %0" : "=m"(gdtr));
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__asm__ volatile ("sidt %0" : "=m"(idtr));
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T = (uint32_t)g_tramp_page;
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page = (uint8_t *)(uintptr_t)g_tramp_page;
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for (k = 0; k < len; k++) page[k] = (uint8_t)sk_ap_tramp_start[k];
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*(uint32_t *)(void *)(page + (sk_ap_tr_pm_jmp - sk_ap_tramp_start)) =
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T + (uint32_t)(sk_ap_tr_pm32 - sk_ap_tramp_start);
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*(uint32_t *)(void *)(page + (sk_ap_tr_lm_jmp - sk_ap_tramp_start)) =
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T + (uint32_t)(sk_ap_tr_lm64 - sk_ap_tramp_start);
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*(uint32_t *)(void *)(page + (sk_ap_tr_gdtr - sk_ap_tramp_start) + 2) =
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T + (uint32_t)(sk_ap_tr_gdt - sk_ap_tramp_start);
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d = (ap_tramp_data_t *)(void *)(page + (sk_ap_tr_data - sk_ap_tramp_start));
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d->cr0 = cr0;
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d->cr3 = cr3;
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d->cr4 = cr4;
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d->cr4_boot = cr4 & ~CR4_PCIDE;
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d->efer = rdmsr64(0xC0000080u) & ~(1ull << 10); /* LMA is the CPU's to set */
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d->pat = rdmsr64(0x277u);
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d->xcr0_valid = (cr4 & CR4_OSXSAVE) ? 1u : 0u;
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d->xcr0 = 0;
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if (d->xcr0_valid) {
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uint32_t lo, hi;
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__asm__ volatile ("xgetbv" : "=a"(lo), "=d"(hi) : "c"(0));
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d->xcr0 = ((uint64_t)hi << 32) | lo;
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}
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d->percpu = (uint64_t)(uintptr_t)pc;
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d->stack = (uint64_t)(uintptr_t)stack_top;
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d->entry = (uint64_t)(uintptr_t)&sk_smp_secondary_main;
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d->kgdt_limit = gdtr.limit; d->kgdt_base = gdtr.base;
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d->kidt_limit = idtr.limit; d->kidt_base = idtr.base;
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__asm__ volatile ("mfence" ::: "memory");
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if (apic_send_ipi((uint8_t)pc->hw_id, ICR_INIT) != 0) {
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console_println("SMP: INIT IPI not delivered");
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return -1;
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}
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wait_us(10000u);
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(void)apic_send_ipi((uint8_t)pc->hw_id, ICR_STARTUP | (T >> 12));
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wait_us(200u);
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if (!__atomic_load_n(&pc->online, __ATOMIC_ACQUIRE)) {
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(void)apic_send_ipi((uint8_t)pc->hw_id, ICR_STARTUP | (T >> 12));
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}
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return 0;
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}
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