fix(raspi): the Pi 5's native path turns the MMU and caches on before any C; bounded mailbox; framebuffer address from dma-ranges

boards/BRINGUP.md R2/R3, FABRIC-3 SXXXIX.  The entry stub cleans the cache
over the image, builds an identity map (the image's GiB Normal, the rest
Device) and enables MMU and caches at EL2 (or EL1); rpi5_mmu.c makes the
devicetree's RAM Normal and the framebuffer uncached.  Mailbox waits give
up after one second; the buffer is cleaned around the exchange; the
framebuffer address goes through dma-ranges, not a Pi 4 mask.

New rpi5-rehearsal target runs the native image on QEMU virt at EL2.  It
found three more that would each have stopped the board: the PL011 shift
(mine, c9519173; the host test asserted it), the GIC address not carried
through /soc's ranges (new fdt_reg_address(), checked against the real
Pi 5 DTB), and no timer IRQ at EL2 (HCR_EL2.IMO/FMO/AMO).

Rehearsal: POST 1052 passed, same parity hash as UEFI.  Standard acceptance
on three ISAs: POST 1052, hash 0x82f4ae7cb2e2d424.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>

kernel/include/starkernel/rpi5_mmu.h

@@ -0,0 +1,26 @@
+/*
+  StarForth — Steady-State Virtual Machine Runtime
+  Copyright (c) 2023–2026 Robert A. James. All rights reserved.
+  Licensed under the StarForth License, Version 1.0.
+ */
+
+/**
+ * rpi5_mmu.h - the Pi 5 native path's identity map, once C runs
+ * (rpi5_mmu.c; native_rpi5_entry.S turns the MMU on).
+ */
+
+#ifndef STARKERNEL_RPI5_MMU_H
+#define STARKERNEL_RPI5_MMU_H
+
+#include <stdint.h>
+
+/* Makes every further GiB the devicetree's /memory covers entirely Normal
+ * write-back. Returns how many GiB entries changed, or -1 if /memory
+ * cannot be read. */
+int rpi5_mmu_map_ram(const void *dtb);
+
+/* Makes [addr, addr+size) Normal non-cacheable (2 MiB blocks in the first
+ * GiB, a whole GiB above it). Returns 0, or -1 if it cannot. */
+int rpi5_mmu_uncached(uint64_t addr, uint64_t size);
+
+#endif /* STARKERNEL_RPI5_MMU_H */